Person: Parekh, Rutu
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Rutu Parekh
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079-68261553
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Nanoelectronics, Microelectronics, Embedded Systems and IOT
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Dr. Rutu Parekh did her M. Tech in Electrical Engg. from Concordia University, Montreal, Canada, PhD in Electrical Engg. (Nanoelectronics) from Universit� de Sherbrooke, Sherbrooke, Canada and as a Postdoctoral fellow at Centre of Excellence in Nanoelectronics, IIT Bombay in 2015. Her research interest includes developing of models, co-design methodology and co-simulation of hybrid circuits of emerging nanoelectronic devices with CMOS technology, low voltage low power circuits, Phase Change Memory, MEMS devices and embedded systems. She has industrial experience with eInfochips, Ahmedabad and HP Karkland, Montreal, Canada, research experience with Ecole Polytechnic, Quebec, Canada, and teaching experience with Nirma University of Science and Technology, Ahmedabad. She is currently working as an Assistant Professor at DA-IICT, Gandhinagar, India. She has published a number of international journal and conference articles related to her research areas. In addition, she has been offering service as an editorial board member for international journal and technical committee member in numerous international conferences. She is also associated with The Inter-University Centre for Astronomy and Astrophysics, Pune, India, as a Visiting Associate.
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Publication Metadata only Nanoelectronics : Physics, technology and applications(IOP Publishing, Bristol, UK, 2023-12-01) Parekh, Rutu; Parekh, Rutu; Dhavse, Rasika; DA-IICT, GandhinagarPublication Metadata only Design strategy and simulation of single-gate SET for novel SETMOS hybridization(Springer, 03-01-2021) Shah, Raj; Parekh, Rutu; Dhavse, Rasika; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; DA-IICT, GandhinagarThis paper presents a design methodology for a single-gate single-electron transistor (SG-SET) for room temperature operation of SET and hybrid SETMOS circuits. Initially, the SET electrostatics is analytically modeled using a free-energy equation. Tunneling probability is determined by modifying the Mahapatra�Ionescu�Banerjee model. The SET is designed systematically so as to achieve process and supply voltage compatibility with 22-nm CMOS technology. A Si�Al�Si SG-SET with 3-nm ultra-thin tunnel barriers is proposed and simulated with drift-diffusion, Philips unified mobility, and Schenk direct tunneling models. A 1D Schrodinger equation was solved in the critical region that covered two tunnel barriers and a conductive island. The current-voltage characteristic of the SG-SET is plotted to observe a Coulomb blockade of � 0.8 V at room temperature. The tunnel resistance and total island capacitance of the proposed SET for circuit simulations are extracted as 20 M and 0.193 aF, and they are in very close agreement with the analytical values. The tunnel resistance extracted from TCAD simulations is used in the MIB model for validation of SET functionality. Further, we propose the use of this SET in hybrid SETMOS logic implementation at room temperature with ultra-low power consumptionPublication Metadata only Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnectsParekh, Rutu; Agrawal, Yash; Parekh, Rutu; Palaparthy, Vinay; Agrawal, Yash; Pathade, Takshashila; Palaparthy, Vinay; DA-IICT, Gandhinagar; Pathade, TakshashilaRigorous technology scaling of integrated circuits to�nanometer range�aids to acquire prodigious operational speed and versatile functionality in system-on-chip. However, this leads to escalation in interconnect parasitics and non-ideal issues that have become primary bottleneck in the existing copper based on-chip interconnect system. Graphene based�carbon nanotube�bundle has emerged as prospective interconnect for high speed applications. This paper focuses on bundled carbon nanotubes and their different spatial arrangements viz. single wall CNTs (SWCNTs), multiwall CNTs (MWCNTs) and mixed CNT bundles (MCBs). Such�bundle configurations�boost the performance of system in terms of reducing system latency and�power consumption�in addition providing system reliability. The significant novel contribution of this paper lies in executing eye-diagram analysis of the futuristic bundled CNT structures as interconnects. Eye-diagram is an important tool for analysing signal integrity effects. The several performance analyses have been performed in SPICE and ADS EDA tools at 22?nm technology node.Publication Metadata only Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects(Elsevier, 16-02-2021) Pathade, Takshashila; Parekh, Rutu; Parekh, Rutu; Agrawal, Yash; Palaparthy, Vinay; Agrawal, Yash; Palaparthy, Vinay; DA-IICT, Gandhinagar; Pathade, Takshashila (201621013)Rigorous technology scaling of integrated circuits to�nanometer range�aids to acquire prodigious operational speed and versatile functionality in system-on-chip. However, this leads to escalation in interconnect parasitics and non-ideal issues that have become primary bottleneck in the existing copper based on-chip interconnect system. Graphene based�carbon nanotube�bundle has emerged as prospective interconnect for high speed applications. This paper focuses on bundled carbon nanotubes and their different spatial arrangements viz. single wall CNTs (SWCNTs), multiwall CNTs (MWCNTs) and mixed CNT bundles (MCBs). Such�bundle configurations�boost the performance of system in terms of reducing system latency and�power consumption�in addition providing system reliability. The significant novel contribution of this paper lies in executing eye-diagram analysis of the futuristic bundled CNT structures as interconnects. Eye-diagram is an important tool for analysing signal integrity effects. The several performance analyses have been performed in SPICE and ADS EDA tools at 22?nm technology node.Publication Metadata only Design and implementation of single electron transistor based 8X8 bit signed multipliers(Elsevier) Shah, Chintan; Shah, Raj; Dhavse, Rasika; Parekh, Rutua; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; DA-IICT, Gandhinagar; Shah, Chintan (201611031)Single electron transistor (SET) has several advantages over CMOS such as it is highly scalable and has ultra-low power consumption. It has emerged as a promising technology to be used as a building blocks for next generation integrated circuit design. In this paper, prospective and efficient implementation of high speed, low power and extremely compact digital multipliers using SET is proposed for the first time. For effective analysis and comparison, three different 8-bit signed multipliers such as Baugh Wooley, Booth and Array multiplier have been designed and their simulation results are validated using the Cadence Virtuoso ADE tool. Performance comparison in terms of power and delay between SET and 16?nm CMOS is evaluated. From the simulation results, it is observed that multipliers based on SET outperforms its CMOS counterpart in all aspects. Considering above mentioned multipliers, SET based Booth multiplier design is having lowest power consumption of 1.41?�W and propagation delay of 6.09?ps as compared to 7.53?�W and 454.94?ps respectively for CMOS counterpart below.Publication Metadata only Simulation and Comparative Study of Resonant Tunneling Diode(Walailak University, 01-08-2022) Shah, Yashvi; Kapoor, Isha; Singhvi, Purva; Birua, Babita; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; DA-IICT, Gandhinagar; Shah, Yashvi (201701045); Kapoor, Isha (201701085); Singhvi, Purva (201701039); Birua, Babita (201701112)This paper studies and investigates the effect of physical and electrical parameters on double, triple and six barrier resonant tunneling diodes (RTD). The materials used for quantum well and barriers are Gallium arsenide (GaAs) and Aluminium gallium arsenide (AlGaAs), respectively. The parameters that were reasoned and studied include conduction band, current density, transmission coefficient and resonance energy. The above parameters were studied by changing bias voltage, temperature, barrier width and doping concentration. From the simulations performed it is observed that for double barrier RTD the peak current density is observed at 0.2 V and the valley current density is observed at 0.3 V, whereas for a triple barrier RTD the peak current density is observed at 0.015 V and the valley current density is observed at 0.06 V. The value of transmission coefficient for double barrier RTD decreases especially after bias applied is more than resonant bias (0.2 V). The effect of increasing bias leads to a decrease in the resonance level in the conduction band. The width of resonance energy decreases with the increase in barrier width.�With increase in number of barrier the number of resonance level increases which leads to an increasing peaks in the transmission coefficient curve. The effect of increasing temperature leads to higher current and more resonance energy. With the thickening of barrier width, less transmission of electrons occurs leading to a reduced current density. When the barriers are increased the negative differential region (NDR) is achieved at low voltages.Publication Metadata only A Novel Slice-Based High-Performance ALU Design Using Prospective Single Electron Transistor(Taylor & Francis, 01-03-2022) Patel, Rashmit; Parekh, Rutu; Agrawal, Yash; Parekh, Rutu; Agrawal, Yash; DA-IICT, GandhinagarThe arithmetic logic unit (ALU) is one of the most essential components of any microprocessor or computing system that is capable of performing several arithmetic as well as logic operations. For realizing efficient and high-performance ALU, proper designing, optimum selection of materials and incorporation of advanced devices are utmost important. The single electron transistor (SET) is a prominent advanced device structure for achieving high-end computing system. In this paper, the prospective SET-based ALU is realized to meet next-generation requirements like higher speed, lower power, and volume. Also, the enhancement capability of ALU can be further accomplished by incorporating effective modular design using slice-based approach. The slice-based design approach provides simplicity and extensibility of the design. In this, each slice has the capability to perform arithmetic and logical operations on one-bit input data. Henceforth, cascading of�n�such slices generates the�n-bit ALU. The multiplication operation is executed separately. The incorporation of separate multiplier block aids in achieving fast execution of multiplication operation with a single instruction. The performance of high-end proposed SET-based ALU is compared with the conventional complementary metal oxide semiconductor (CMOS) and 18?nm FinFET technology-based ALU designs. It is observed that the SET-based ALU gives 1.9� lesser delay and 19.8� lower power dissipation as compared to its 16?nm CMOS counterpart. Also, with respect to 18?nm FinFET-based technology, proposed SET-based design out-stands extensively in terms of lower transistor count and power.Publication Metadata only Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature(UTHM, 12-09-2019) Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; Parekh, Rutu; DA-IICT, GandhinagarHeterogeneous 3D integration of single electron transistor (SET) circuits with CMOS based circuits is achieved by stacking a SET layer above CMOS IC. Low power and delay efficient circuits can be designed using SET. In this paper, we have designed and simulated 6T SRAM array operating at room temperature and at CMOS comparable voltage. Peripheral circuit like sense amplifier, decoder, write circuit and pre-charge circuit using SET have been designed for optimum performance. The stability of 6T SRAM cell is verified using N-curve method. The designed SET based 8 x 8 bit SRAM is 99.54 % power efficient, 92.19 % faster in write access time and 78.58 % faster in read access time compared to 16 nm CMOS based SRAM. The SRAM is designed to work at CMOS comparable voltage of 800 mV, which can be scaled up to 20 mV with better efficiency. The designed SRAM is tested and verified for variation in process, voltage and temperature. The maximum frequency of operation for the designed SET based SRAM with memory controller is 4 GHz.Publication Metadata only Neural Network-based Fast and Intelligent Signal Integrity Assessment Model for Emerging MWCNT Bundle On-Chip Interconnects in Integrated Circuit(Taylor & Francis, 26-02-2023) Bhatti, Gulafsha; Pathade, Takshashila; Agrawal, Yash; Palaparthy, Vinay; Gohel, Bakul; Parekh, Rutu; Kumar, Mekala Girish; DA-IICT, Gandhinagar; Gulafsha Bhatti (202021005); Takshashila Pathade (201621013)At nanometer technology nodes, the efficient signal integrity and performance assessment of vast on-chip interconnects are crucial and challenging. For a long time, copper (Cu) has been used as an interconnect material in integrated circuits (ICs). However, as heading towards lower technology nodes, Cu is becoming inadequate to satisfy the requirements for high-speed applications due to its physical limitations. To mitigate this issue, a multiwall carbon nanotube bundle (MWCNTB) is proven to be a better replacement for Cu. Hence, the current work innovatively focuses on modeling, analysis, and performance evaluation of MWCNTB interconnects at 32?nm technology nodes using various machine learning (ML) and neural network (NN) based techniques for signal integrity assessment and fast computation of on-chip interconnect design. Based on the results obtained by comparing the different performance parameters, it is envisaged that NN-based ADAM technique leads to the best-suited model. The developed model is fruitful in evaluating the output performance of the system, such as power-delay-product (PDP), performing parametric analysis, and predicting optimum input design parameters of the driver-interconnect-load (DIL) system. This work utilizes HSPICE and Python electronic design automation tools for its implementation.Publication Metadata only Single-electron transistor: review in perspective of theory, modelling, design and fabrication(Springer, 01-05-2021) Agrawal, Yash; Patel, Rashmit; Parekh, Rutu; Agrawal, Yash; Parekh, Rutu; DA-IICT, GandhinagarIntegrated circuit (IC) technology has grown tremendously over the last few decades. The prime goal has been to achieve low-power and high-performance in logic and memory devices with minimal footprint. This has lead to continuous scaling of devices and interconnects over silicon chips. Scaling of technology plays an important role for improvement of IC performance in terms of delay, signal-integrity and power-dissipation. Novel devices like FinFET, nano-electromechanical systems, graphene-FETs and single-electron transistor (SET) offer several advantages over various shortcomings of scaling. The future of IC industry is proposed to be heterogeneous 3D integration of different technologies. A SET is a potential nano device that works on quantum mechanical principle and can be co-integrated with the widely adopted complementary metal-oxide semiconductor technology to enhance its performance at scaled technology nodes. To explore the feasibility of SET, an extensive literature review has been carried out in this paper. The literature review comprises comprehensively research work related to SET theory, design and fabrication. Also, the SET based computing system design is presented for room temperature operation. The extensive literature review and thereafter execution of varying analyses reveal that the SET is a potential nano-device for futuristic applications.