A Novel Slice-Based High-Performance ALU Design Using Prospective Single Electron Transistor

Abstract

The arithmetic logic unit (ALU) is one of the most essential components of any microprocessor or computing system that is capable of performing several arithmetic as well as logic operations. For realizing efficient and high-performance ALU, proper designing, optimum selection of materials and incorporation of advanced devices are utmost important. The single electron transistor (SET) is a prominent advanced device structure for achieving high-end computing system. In this paper, the prospective SET-based ALU is realized to meet next-generation requirements like higher speed, lower power, and volume. Also, the enhancement capability of ALU can be further accomplished by incorporating effective modular design using slice-based approach. The slice-based design approach provides simplicity and extensibility of the design. In this, each slice has the capability to perform arithmetic and logical operations on one-bit input data. Henceforth, cascading of�n�such slices generates the�n-bit ALU. The multiplication operation is executed separately. The incorporation of separate multiplier block aids in achieving fast execution of multiplication operation with a single instruction. The performance of high-end proposed SET-based ALU is compared with the conventional complementary metal oxide semiconductor (CMOS) and 18?nm FinFET technology-based ALU designs. It is observed that the SET-based ALU gives 1.9� lesser delay and 19.8� lower power dissipation as compared to its 16?nm CMOS counterpart. Also, with respect to 18?nm FinFET-based technology, proposed SET-based design out-stands extensively in terms of lower transistor count and power.