Design strategy and simulation of single-gate SET for novel SETMOS hybridization

Abstract

This paper presents a design methodology for a single-gate single-electron transistor (SG-SET) for room temperature operation of SET and hybrid SETMOS circuits. Initially, the SET electrostatics is analytically modeled using a free-energy equation. Tunneling probability is determined by modifying the Mahapatra�Ionescu�Banerjee model. The SET is designed systematically so as to achieve process and supply voltage compatibility with 22-nm CMOS technology. A Si�Al�Si SG-SET with 3-nm ultra-thin tunnel barriers is proposed and simulated with drift-diffusion, Philips unified mobility, and Schenk direct tunneling models. A 1D Schrodinger equation was solved in the critical region that covered two tunnel barriers and a conductive island. The current-voltage characteristic of the SG-SET is plotted to observe a Coulomb blockade of � 0.8 V at room temperature. The tunnel resistance and total island capacitance of the proposed SET for circuit simulations are extracted as 20 M and 0.193 aF, and they are in very close agreement with the analytical values. The tunnel resistance extracted from TCAD simulations is used in the MIB model for validation of SET functionality. Further, we propose the use of this SET in hybrid SETMOS logic implementation at room temperature with ultra-low power consumption