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Design strategy and simulation of single-gate SET for novel SETMOS hybridization

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dc.contributor.affiliationDA-IICT, Gandhinagar
dc.contributor.authorShah, Raj
dc.contributor.authorParekh, Rutu
dc.contributor.authorDhavse, Rasika
dc.contributor.authorParekh, Rutu
dc.contributor.authorParekh, Rutu
dc.contributor.authorParekh, Rutu
dc.contributor.authorParekh, Rutu
dc.contributor.authorParekh, Rutu
dc.date.accessioned2025-08-01T13:09:19Z
dc.date.issued03-01-2021
dc.format.extent218-229
dc.identifier.citationRaj Shah, Parekh, Rutu& Rasika Dhavse "Design strategy and simulation of single-gate SET for novel SETMOS hybridization," Journal of Computational Electronics, Springer, vol. 20, issue. 1, ISSN: 15698025, pp. 218-229, 2021, doi: 10.1007/s10825-020-01622-2.
dc.identifier.doihttps://doi.org/10.1007/s10825-020-01622-2
dc.identifier.issn1572-8137
dc.identifier.scopus2-s2.0-85098666660
dc.identifier.urihttps://ir.daiict.ac.in/handle/dau.ir/1834
dc.identifier.wosWOS:000604491900002
dc.publisherSpringer
dc.relation.ispartofseriesVol. 20; No. 1
dc.source Journal of Computational Electronics
dc.source.urihttps://link.springer.com/article/10.1007/s10825-020-01622-2
dc.titleDesign strategy and simulation of single-gate SET for novel SETMOS hybridization
dspace.entity.typePublication
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