Theses and Dissertations
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Item Open Access Investigating into a light-weight reconfigurable VLSI architecture for biomedical signal processing applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2019) Jain, Nupur; Mishra, BiswajitThe Body Sensor Network systems consist of signal acquisition and processing blocks along with Power Management Unit and radio transmission capabilities. The high power consumption of the radio transmission is often eliminated by adopting the on-node processing through signal processing platform with increased computation ability. Dedicated hardware accelerators optimized for operations predominantly seen in biomedical signal processing algorithms are oftenused in tandem with a microprocessor for this purpose. However, they do not support further algorithm improvements and optimizations owing to their dedicated nature. The benefits of configurability can be found in reconfigurable architectures at the cost of reconfiguration overheads. The shift-accumulate architecture developed in this thesis leverage the regularity in dominant functions in biomedical signal processing and thereby yields gate count advantages. The configurable datapath of the architecture renders multiple DSP operation emulation by means of mapping methodologies developed for efficient realization in terms of hardware utilization and memory accesses. The architecture exhibits various topologies which further supports efficient function realization. The configuration scheme of the architecture is developed which effectively consist of control word and tightly coupled data memory. The architecture is realized on a Filed Programmable Gate Array (FPGA) platform demonstrating the target function emulation and hardware results are compared with ideal outcomes. The Video Graphics Array (VGA) and Universal Asynchronous Receiver Transmitter (UART) interface controllers are developed in this work for error quantification and analysis. The architecture contains a 6 6 array of functional units having shift-accumulate as its underlying operation and has gate count of 25k and 46.9 MHz operating frequency while emulating 36-tap FIR, CORDIC, DCT, DWT, moving average, squaring and differentiation functions. Generally, biomedical signal processing functions include multiple stages consisting of noise removal, feature detection and extraction etc. The on-the-fly reconfigurability is incorporated into the architecture that leverage the low input datarates of biosignals. The architecture reconfigures dynamically while realizing different functions of the signal chain. The memory adapts to the incoming target function and supports 7 functions in its present structure. However, the architecture and memory remains scalable. Pan-Tompkins Algorithm based QRS detection realization is demonstrated on the architecture using the reconfigurability. This work offers 4 reduced area and 2.3 increase in performance with respect to the existing contemporary literatures.Item Open Access Measurement of complex permittivity of materials using rectangular dielectric wave guide (RDWG) technique in 5.85-8.20 Ghz range(Dhirubhai Ambani Institute of Information and Communication Technology, 2018) Rout, Debadutta; Ghodgaonkar, DeepakThe Rectangular DielectricWaveguide (RDWG)Technique is an efficient technique developed for the measurement of complex permittivity of materials of various thickness and cross sectional areas over various frequency ranges by measuring the S-parameters of the device under test.In this project RDWG technique has been used along with Through- Reflect-Line(TRL) calibration to measure the complex permittivity of materials in 5.85 to 8.20GHz frequency range.Permittivity of various samples are measured with the help of S-parameters and the obtained values of permittivity is compared with the theoretically available value.The results obtained by the RDWD technique is seen to be very close to the theoretically available values and suggestions to improve the accuracy of the technique is also provided..Item Open Access CTS and CCOpt metodology's to achieve low skew-low power clock.(Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Sreekanth, M.; Bhatt, AmitIn synchronous VLSI chips, clock distribution network plays an important role. The quality of clock network mainly effects the performance of the chip, because the speed of data transfer depends on clock signal. Achieving minimum clock latency and clock skew becomes difficult when we have clock signals in terms of 100MHz. in the clock network, skew is one of the major concerns because of this clock rate decreases. In this document, the main focus is on Clock Tree Synthesis (CTS) methodology for achieving low skew. Primarily CTS requires inputs like target skew, maximum delay, minimum delay. In this report we analyze the effect of these parameters on achieving low skew and low power clock. Then we will try to make a generalized conclusion to get low-skew and low power CTS. Due to on-chip variation, low power and design complexity, clock timing in diverging as technology shrinks down below 45 nm. As transistor goes below 45 nm technology, the timing gap becomes very severe as it reaches up to 50%. Clock Concurrent Optimization is a new approach which merger physical optimization into CTS and optimizes both clock delays and logic delays simultaneously. In this report we will discuss how CCOpt optimizes both logic and clock simultaneously. In addition to that we will discuss the key benefits of CCOpt when compared to CTS.Item Open Access Study of power in CR-SRAM in context of precharge reference voltage.(Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Rupapara, Kripal D.; Zaveri, Mazad SIn Morden times power dissipation in electronic circuits has become more important due to increase use of portable and handheld devices. Increased operating frequency results in more power consumption in almost every VLSI circuits. Scaling in integrated circuit technology directly paves way to increased package density, thereby increasing on chip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. Large fraction of power is consumed by memory circuits, if we can reduce power consumed by memory structure can reduce overall power consumption. This thesis is mainly concentrated on various components of power consumption in digital circuits, operation of SRAM, various technique to reduce power in SRAM and finally illustrates charge recycling SRAM for lower power consumption.Item Open Access Novel 7T SRAM cell design for low power cache applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Joshi, Srawan Kumar; NagChoudhuri, DipankarScaling in integrated circuit technology directly paves way to increased package density, thereby increasing onchip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. SRAM is used as on chip cache memory. A major part of the power consumption in any memory architecture is due to charging and discharging of highly capacitive bitlines and wordlines. Existing techniques mainly concentrated on the reduction of power due to the capacitive bitlines and wordlines. In this thesis, a new 7T SRAM cell has been proposed with a single bitline architecture which reduces the dynamic power consumption to a great extent. This proposed design resulted in power reduction of write ‘0’ and read ‘0’ operation, based on the fact that the majority of the cache writes are 0’s. A memory array of size 256Kb (512x512) was designed using the basic 6T SRAM and propsed 7T SRAM cell to carry out the simulations and compare the results for power optimization. The simulations were done using Cadence Virtuoso (ADE) tool in gpdk180 library using 0.18μm technology. With the proposed SRAM cell implementing 256Kb memory array, reduction of write power (approximately 80%) and read power (approximately 55%) is achieved compared to conventional SRAM array. There is an area overhead of 28.76% using the present 180nm technology.Item Open Access Design & layout of a low voltage folding & interpolation ADC for high speed applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Tiwari, Sandeep Kumar; Sen, SubhajitAnalog to Digital Converters (ADC) and Digital to Analog Converters (DAC) plays a vital role in mixed analog signalling, communication and digital signal processing world. Now a day, the demand for designing of high speed, low power and low voltage ADCs are increasing tremendously in high speed data processing applications. In the folding and interpolation ADCs folding amplifiers have the serious bandwidth limitation problem because of larger parasitic capacitance and resistance at the output node. In this thesis work a low voltage and high speed folding and interpolation ADC is implemented using current steering CMOS folding amplifier followed by transresistance amplifier (TRA) in UMC 180nm CMOS technology. The current steering folding amplifier significantly reduces power as well as number of tail current sources compared to the conventional folding amplifier. Transresistance amplifier, which is connected at the output of folding amplifier, avoids the analog bandwidth limitation problem. MSB and LSB bits are generated simultaneously at the output therefore sample and hold circuit is not required in this architecture. This proposed circuit works at 1.8V power supply and 85 MSamples/S and consumes 70mW power. Simulation and Layout of Folding and Interpolation ADC were done using UMC CMOS 180nm technology in the Cadence Analog Design EnvironmentItem Open Access Transaction based verification of multimedia IP(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Shah, Hirav; Dubey, RahulVerification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debugging at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. Design under test (DUT) operates at a binary stimulus level (e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The JPEG Encoder Intellectual Property (IP) core is used as a DUT. This IP is taken from opencores.org website. Whole system is verified on ZeBu emulator.Item Open Access Study of the effectiveness of various low power techniques on sequential and combinational gate dominated designs(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Rana, Kunj; Bhatt, AmitIn last decade, the technological advancement is seen in semiconductor field like never before. The need for low power has caused a major paradigm shift where power dissipation has become as important consideration as performance and area. The size of the electronic equipments is getting smaller and smaller which requires smaller integrated circuits (ICs). Due to this the power consumption happens to be a major concern in developing the smaller ICs. The objective of the dissertation is to develop a low power digital design flow using Cadence® tools. This report discusses various strategies and methods for designing low power circuits and systems. It describes the many issues facing designers at various levels and presents some of the techniques that have been proposed to overcome these difficulties. To do this, particular RTL (Verilog code) is taken for some design. First various floorplans are tested on the design for better power number then using the same design, analysis on two different interconnect estimation model is done. Finally using the floorplan and interconnect estimation model analysis results low power implementation is done for the same design which is passed through various steps of digital design flow like synthesis, floor planning, placement, routing, and converted to GDSII (Graphic Database System) file format which can be directly sent to foundry. In low power implementation several techniques like clock gating, operand isolation, and multi Vt cells are used with some enhancement switches provided by the toolItem Open Access Asynchronous analog to digital converter(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Patel, Vidyut A.; Parikh, Chetan D.Nowadays, asynchronous systems are becoming more popular for low power applications. Asynchronous Systems help to reduce metastability errors and clock skew errors. This thesis is about an asynchronous analog to digital converter (ADC) designed for low power. Here, a design is proposed based on successive approximation algorithm with folding circuit. The folding circuit works as a voltage mapping circuit. The proposed ADC can be used with asynchronous systems as well as conventional synchronous systems. The ADC has been implemented for 5 bit resolution for input voltage range of 0.7V to 2V in 180nm technology. It achieves maximum speed of 8MSPS and DNL of 0.5LSB. The power consumption of the ADC is 2.6mW.Item Open Access Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Chevella, Subhash; Parikh, Chetan D.This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the residue amplifier used in the designing of the pipelined ADC. So, designing of accurate gain switched capacitor (SC) amplifier is an important concern. The gain accuracy of SC amplifier depends upon the MOS switches, capacitance mismatch and operational amplifier. Among these three, the accuracy will be affected more due to the mismatch of the capacitance values. This thesis is more concentrated on capacitance mismatch. I proposed a switched capacitor amplifier whose gain is less sensitive to capacitance mismatch as compared to conventional switched capacitor amplifier. The percentage of error variation of the gain due to mismatch in proposed circuit varies from 2.1% to 2.9% but in conventional amplifier it varies from -5.1% ~ 8.5%. Proposed circuit has an improvement of 5.6%. All these simulation have done using 180nm technology in LT Spice.