CTS and CCOpt metodology's to achieve low skew-low power clock.

Abstract

In synchronous VLSI chips, clock distribution network plays an important role. The quality of clock network mainly effects the performance of the chip, because the speed of data transfer depends on clock signal. Achieving minimum clock latency and clock skew becomes difficult when we have clock signals in terms of 100MHz. in the clock network, skew is one of the major concerns because of this clock rate decreases. In this document, the main focus is on Clock Tree Synthesis (CTS) methodology for achieving low skew. Primarily CTS requires inputs like target skew, maximum delay, minimum delay. In this report we analyze the effect of these parameters on achieving low skew and low power clock. Then we will try to make a generalized conclusion to get low-skew and low power CTS. Due to on-chip variation, low power and design complexity, clock timing in diverging as technology shrinks down below 45 nm. As transistor goes below 45 nm technology, the timing gap becomes very severe as it reaches up to 50%. Clock Concurrent Optimization is a new approach which merger physical optimization into CTS and optimizes both clock delays and logic delays simultaneously. In this report we will discuss how CCOpt optimizes both logic and clock simultaneously. In addition to that we will discuss the key benefits of CCOpt when compared to CTS.