M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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    High Performance Computing
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2016) Patel, Jaykumar; Bhatt, Amit
    Technology today has evolved from the Mainframe computers to laptops to small and smart handheld devices. These smart end devices are accompanied with extremely robust ARM 64-bit processors which are a perfect blend of power andperformance balancing. It becomes extremely important to utilize their capabilitiesto the maximum. The thesis is on High Performance Computing whichexploits the possibilities of performing computationally intensive tasks by clusterformation of easily available commodities off-the-shelf. The high performancecomputing clusters using Linux (Linaro) operating systems based Qualcomm embeddedboards, Linux desktop computers, andWindows desktop computers havebeen created. High Performance Linpack benchmarks are ran on the Linux basedclusters and the expected speedup in performance is obtained thereby allowingformation of a very cheap and high throughput computing cluster using devicesavailable around us and no need of specialized supercomputing environment.This idea of networking cluster formation is further extended to cloud. The samekind of computing cluster has been created on Amazon cloud services and hasbeen successfully tested for its throughput using HPL benchmarks. Now, the ideawas to integrate the local clusters with the clusters on cloud so that the live videoprocessing based computationally and power intensive tasks can be solved locallyfirst and then clusters on cloud can be used when the processing and batterypower of the local devices gets exhausted in real time. Thus, the idea of clusterformation can be extended to the field of IoT for solving small data issues like batterypower and processing power capacity in domains involving applications likeextensive video processing, modelling of complex mathematical equations, solvingcomplex input and computationally intensive machine learning algorithmsand many more applications
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    Implementation of different branch prediction schemes on FabScalar generated superscalar processor
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2014) Patel, Jayesh; Bhatt, Amit
    Performance of modern pipeline processor depends on steady flow of useful instruction for processing. Branch instruction in the program disrupts the sequential flow of instruction by presenting multiple paths through which program may proceed. By predicting branch outcome early, branch predictor allows processor to continue fetching instruction from the predicted path. As the computer architecture try to squeeze more performance out of superscalar processor by increasing issue widths and pipeline depths. At that time penalties due to branch instruction continue to rise. Because of high branch miss prediction penalty, the branch prediction accuracy is a very important factor for superscalar processor. This study is concerned about exploring a FabScalar Tool for automatically generating superscalar cores of different pipeline widths, depths and sizes. This tool provides the RTL code of the desired superscalar core. A four issue wide superscalar core is generated using FabScalar tool. On this superscalar core the implementation and comparative study of three different dynamic branch predictions technique is done. These techniques are Bimodal Branch Predictor, Two-way Correlating Branch Predictor and Hybrid Branch Predictor.
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    Implementation of high speed serial communication blocks
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Parekh, Devang Tarunkumar; Dubey, Rahul
    Serial communication is widely being used from PCs to handheld mobile phones due to very less hardware, low cost, easier design process in comparison to parallel communication. For bit by bit, reliable transmission and receiving at the physical layer it is important for data sequences to have high transition density, low power spectral density, less bit error and reduced bandwidth. This thesis implements the universal serial bus 2.0 (USB 2.0) transceiver Macro cell interface (UTMI) in a generic form to use different low level signaling protocol blocks in other serial communication standards. The code written is synthesizable and verified for correct functionality. The HDL code is a state machine (Mealy machine) implementation from the specification of UTMI. The challenging part of the work was to implement clock and data recovery block as it involved a lot of engineering concepts like control theory, digital electronics and analog circuits. The work presents intricacies in the design of PLL for recovery of clock and data. UTMI helps in faster development of ASIC and provides an abstraction layer for the peripheral developers who are not involved in low level details of physical layer. Finally the results for UTMI implementation are presented.
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    Design of a high speed I/O buffer
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Rathore, Akhil; Parikh, Chetan D.
    In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. CML buffers achieves high speed due to low output voltage swing which reduces transition time. Presently CML buffers are designed with differential architecture and uses different bandwidth extension technique (inductive peaking, negative miller capacitance, active feedback) to increase the speed. At high frequency, input output coupling limits the bandwidth due to miller effect because of gate to drain capacitance. The proposed design incorporates the architecture which reduces miller effect, hence achieves high bandwidth. In this topology a source follower drives a common-gate stage which is an example of ‘unilateral’ amplifier, that is, one in which signal can flow only in one way over large bandwidths. It reduces unintended and undesired feedback. This CML buffer is designed for OC-192/STM-64 application to be used in limiting amplifier which is a critical block in optical system. OC-192/STM-64 works around 10Gbps.