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  4. Implementation of high speed serial communication blocks

Implementation of high speed serial communication blocks

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200811038.pdf (884.08 KB)

Date

2010

Authors

Parekh, Devang Tarunkumar

Journal Title

Journal ISSN

Volume Title

Publisher

Dhirubhai Ambani Institute of Information and Communication Technology

Abstract

Serial communication is widely being used from PCs to handheld mobile phones due to very less hardware, low cost, easier design process in comparison to parallel communication. For bit by bit, reliable transmission and receiving at the physical layer it is important for data sequences to have high transition density, low power spectral density, less bit error and reduced bandwidth. This thesis implements the universal serial bus 2.0 (USB 2.0) transceiver Macro cell interface (UTMI) in a generic form to use different low level signaling protocol blocks in other serial communication standards. The code written is synthesizable and verified for correct functionality. The HDL code is a state machine (Mealy machine) implementation from the specification of UTMI. The challenging part of the work was to implement clock and data recovery block as it involved a lot of engineering concepts like control theory, digital electronics and analog circuits. The work presents intricacies in the design of PLL for recovery of clock and data. UTMI helps in faster development of ASIC and provides an abstraction layer for the peripheral developers who are not involved in low level details of physical layer. Finally the results for UTMI implementation are presented.

Description

Keywords

Microcomputers, Buses, Universal Serial Bus, Computer bus, Computer architecture, UTMI, Exchaning data, Data transmission

Citation

Parekh, Devang Tarunkumar (2010). Implementation of high speed serial communication blocks. Dhirubhai Ambani Institute of Information and Communication Technology, x, 39 p. (Acc.No: T00270)

URI

http://ir.daiict.ac.in/handle/123456789/307

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M Tech Dissertations

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