Publications
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Publication Metadata only Reliability Assessment using Electrical and Mechanical Characterization of Stretchable Interconnects on Ultrathin Elastomer for Emerging Flexible Electronics System(IEEE, 10-07-2025) Bhatti, Gulafsha; Sharma, Rohit; Kumar, Mekala Girish; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, GandhinagarPublication Metadata only In-House Developed Graphene-Based Leaf Wetness Sensor With Enhanced Stability(IEEE, 01-06-2025) Patle, Kamlesh; Yogi, Pooja; Maru, Devkaran; Palaparthy, Vinay; Moez, Kambiz; Agrawal, Yash; DA-IICT, GandhinagarPublication Metadata only Essential Frequency Analysis for Stacked Cu-CNT Composite Cells of TSVs(IEEE, 04-03-2025) Kumar, Mekala Girish; Agrawal, Yash; Pulluri, Harish; Sharma, Rohit; DA-IICT, GandhinagarPublication Metadata only Signal Integrity Analysis of Biodegradable Stretchable Interconnect for Wearable Application(IEEE, 01-07-2025) Bhatti, Gulafsha; Maru, Devkaran; Patle, Kamlesh; Shah, Kinnaree; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, GandhinagarPublication Metadata only Explicit Analytical Model of Stretchable Interconnects for Flexible Electronics System(IEEE, 24-07-2025) Bhatti, Gulafsha; Kumar, Mekala Girish; Sharma, Rohit; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, GandhinagarA printed circuit board (PCB) is one of the strong backbones to execute electronic system designs. Due to fast and reliable communication requirements between integrated circuit and other peripheral components over the PCB, there is a quest for the development of board-level designs and layouts. The advancement in technology has led to inventions from conventional rigid to flexible PCBs or flexible electronics (FE). The conformability of FE circuitry majorly depends upon the stretchable interconnects. An interconnect is the medium through which a signal is transmitted. The characteristic of stretchable interconnects is determined through their electrical and mechanical properties. The analytical model and parasitic extraction of the interconnect for rigid PCB structures have been widely explored earlier. However, the analytical formulation of the stretchable interconnect still remains a challenge and meagerly explored till date. Consequently, in this work, an explicit analytical model for the parasitic extraction of stretchable interconnects, viz., resistance (R), inductance (L), and capacitance (C), under stretching and bending effects has been novelly proposed. Five different interconnect materials have been considered for the analysis. The analytical model results have been validated with the ANSYS EDA tool. It is investigated that the proposed analytical model results are in very close agreement with the ANSYS results for all the considered cases.Publication Metadata only Impact of Electrode Patterns Variation on the Response Characteristic of Leaf Wetness Sensors(IEEE, 05-08-2024) Patle, Kamlesh S; Sharma, Neha; Khaparde, Priyanka; Varshney, Harsh; Bhatti, Gulafsha; Agrawal, Yash; Palaparthy, Vinay; DA-IICT, Gandhinagar; Patle, Kamlesh S(202121017); Sharma, Neha (202211051); Varshney, Harsh (202211001); Bhatti, Gulafsha (202021005)Prediction of plant diseases is essential to reduce crop loss. Early disease prediction models have been investigated for this purpose, where data on leaf wetness duration (LWD) is one of the key components. Leaf wetness sensors (LWSs) are used to better understand how foliar wetness affects plant disease cycles and epidemic development. LWS can be fabricated on printed circuit boards (PCBs), where interdigitated electrode patterns are widely used. However, it is important to understand the efficacy of these patterns for in-situ measurements. For this purpose, in this work, we have fabricated three different patterns viz. circular, oval, and rectangular on the PCB and tested their efficacy during lab and field measurements. Lab measurements indicate that the circular patterned LWS offers a sensitivity of about 1600% over the dry-to-wet range, which is about 2 and 1.5 times more than oval and rectangular patterns, respectively. Besides this, circular patterned LWS offers the hysteresis of about 2%, whereas the oval and rectangular patterned LWS show about 3% and 7%, respectively. Field measurement results specify that circular patterned LWS and commercial LWS Phytos 31 indicate the same number of LWD events. However, oval and rectangular patterned LWS shows extra false events.Publication Metadata only Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects(Elsevier, 16-02-2021) Pathade, Takshashila; Parekh, Rutu; Parekh, Rutu; Agrawal, Yash; Palaparthy, Vinay; Agrawal, Yash; Palaparthy, Vinay; DA-IICT, Gandhinagar; Pathade, Takshashila (201621013)Rigorous technology scaling of integrated circuits to�nanometer range�aids to acquire prodigious operational speed and versatile functionality in system-on-chip. However, this leads to escalation in interconnect parasitics and non-ideal issues that have become primary bottleneck in the existing copper based on-chip interconnect system. Graphene based�carbon nanotube�bundle has emerged as prospective interconnect for high speed applications. This paper focuses on bundled carbon nanotubes and their different spatial arrangements viz. single wall CNTs (SWCNTs), multiwall CNTs (MWCNTs) and mixed CNT bundles (MCBs). Such�bundle configurations�boost the performance of system in terms of reducing system latency and�power consumption�in addition providing system reliability. The significant novel contribution of this paper lies in executing eye-diagram analysis of the futuristic bundled CNT structures as interconnects. Eye-diagram is an important tool for analysing signal integrity effects. The several performance analyses have been performed in SPICE and ADS EDA tools at 22?nm technology node.Publication Metadata only Neural Network-based Fast and Intelligent Signal Integrity Assessment Model for Emerging MWCNT Bundle On-Chip Interconnects in Integrated Circuit(Taylor & Francis, 26-02-2023) Bhatti, Gulafsha; Pathade, Takshashila; Agrawal, Yash; Palaparthy, Vinay; Gohel, Bakul; Parekh, Rutu; Kumar, Mekala Girish; DA-IICT, Gandhinagar; Gulafsha Bhatti (202021005); Takshashila Pathade (201621013)At nanometer technology nodes, the efficient signal integrity and performance assessment of vast on-chip interconnects are crucial and challenging. For a long time, copper (Cu) has been used as an interconnect material in integrated circuits (ICs). However, as heading towards lower technology nodes, Cu is becoming inadequate to satisfy the requirements for high-speed applications due to its physical limitations. To mitigate this issue, a multiwall carbon nanotube bundle (MWCNTB) is proven to be a better replacement for Cu. Hence, the current work innovatively focuses on modeling, analysis, and performance evaluation of MWCNTB interconnects at 32?nm technology nodes using various machine learning (ML) and neural network (NN) based techniques for signal integrity assessment and fast computation of on-chip interconnect design. Based on the results obtained by comparing the different performance parameters, it is envisaged that NN-based ADAM technique leads to the best-suited model. The developed model is fruitful in evaluating the output performance of the system, such as power-delay-product (PDP), performing parametric analysis, and predicting optimum input design parameters of the driver-interconnect-load (DIL) system. This work utilizes HSPICE and Python electronic design automation tools for its implementation.Publication Metadata only Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization(IEEE, 11-02-2021) Pathade, Takshashila; Kumar, Mekala Girish; Parekh, Rutu; Agrawal, Yash; Parekh, Rutu; Agrawal, Yash; DA-IICT, Gandhinagar; Pathade, Takshashila (201621013)The emerging VLSI technology and simultaneously highly dense packaging of devices and interconnects in nano-scale chips have prosperously enabled realization of system-on-chip designs and advanced high-performance computing applications. Concurrently, these have aggravated inevitable challenges in miniaturized integrated circuits (ICs). One of the main limiters in the performance of high-speed VLSI designs is the on-chip interconnects. The emerging graphene based mixed carbon nanotube bundle (MCNTB) interconnects have been investigated as one of the most suited and physically realizable on-chip structure. The present work focuses on utilization of MCNTB as nano-interconnects in the optimized way. Determining optimized placement of CNTs in MCNTB configuration is tedious, skilful task and meagerly explored till date. This has been innovatively taken-up in the current work. In the present paper, novel and efficient particle swarm optimization (PSO) technique is explored and innovatively incorporated to obtain optimal distribution of CNTs in a given rectangular area. The objective function considered for the design is to maximize the tube density. Several signal integrity analyses have been executed. The proposed optimized mixed CNT bundle structure is compared with other different configurations of CNT bundle structures. It is analyzed that the proposed optimized MCNTB configuration produces highly favorable results and is apt suitable for futuristic nano IC designs. The different modelling and performance analyses are performed using MATLAB, SPICE and ADS EDA tools.Publication Metadata only A new tool for simulation of single electron transistor based microprocessor using vector file(2020) Patel, Rashmit; Parekh, Rutu; Agrawal, Yash; Parekh, Rutu; Agrawal, Yash; DA-IICT, Gandhinagar; Patel, Rashmit (201121009)A microprocessor is a general-purpose device, which works on the user defined instructions. The design of next generation microprocessors demands high speed, high density and low power requirements that can be attained by prominent device like Single Electron Transistor (SET). Based on realizable SET parameters at room temperature and 800 mV operating voltage; an 8-bit SET based microprocessor is designed and simulated using Cadence Virtuoso environment. The simulation of the microprocessor requires complex stimuli to verify the design for multiple instructions. Conventionally, the simulation is performed by applying individual signal source to each signal. However, that is not optimum and viable for microprocessor designs. The Cadence Spectre simulator has a facility to simulate the design using vector file, which combines multiple signal sources in a text file. In addition, writing vector file manually is complex and erroneous. To overcome the problem, a tool is designed and developed that generates a vector file for user selected instructions and parameters. The usage of vector file makes the simulation straightforward and accurate. This paper describes the design of a tool for vector file generation.
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