Theses and Dissertations
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Item Open Access Investigating into a light-weight reconfigurable VLSI architecture for biomedical signal processing applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2019) Jain, Nupur; Mishra, BiswajitThe Body Sensor Network systems consist of signal acquisition and processing blocks along with Power Management Unit and radio transmission capabilities. The high power consumption of the radio transmission is often eliminated by adopting the on-node processing through signal processing platform with increased computation ability. Dedicated hardware accelerators optimized for operations predominantly seen in biomedical signal processing algorithms are oftenused in tandem with a microprocessor for this purpose. However, they do not support further algorithm improvements and optimizations owing to their dedicated nature. The benefits of configurability can be found in reconfigurable architectures at the cost of reconfiguration overheads. The shift-accumulate architecture developed in this thesis leverage the regularity in dominant functions in biomedical signal processing and thereby yields gate count advantages. The configurable datapath of the architecture renders multiple DSP operation emulation by means of mapping methodologies developed for efficient realization in terms of hardware utilization and memory accesses. The architecture exhibits various topologies which further supports efficient function realization. The configuration scheme of the architecture is developed which effectively consist of control word and tightly coupled data memory. The architecture is realized on a Filed Programmable Gate Array (FPGA) platform demonstrating the target function emulation and hardware results are compared with ideal outcomes. The Video Graphics Array (VGA) and Universal Asynchronous Receiver Transmitter (UART) interface controllers are developed in this work for error quantification and analysis. The architecture contains a 6 6 array of functional units having shift-accumulate as its underlying operation and has gate count of 25k and 46.9 MHz operating frequency while emulating 36-tap FIR, CORDIC, DCT, DWT, moving average, squaring and differentiation functions. Generally, biomedical signal processing functions include multiple stages consisting of noise removal, feature detection and extraction etc. The on-the-fly reconfigurability is incorporated into the architecture that leverage the low input datarates of biosignals. The architecture reconfigures dynamically while realizing different functions of the signal chain. The memory adapts to the incoming target function and supports 7 functions in its present structure. However, the architecture and memory remains scalable. Pan-Tompkins Algorithm based QRS detection realization is demonstrated on the architecture using the reconfigurability. This work offers 4 reduced area and 2.3 increase in performance with respect to the existing contemporary literatures.Item Open Access CTS and CCOpt metodology's to achieve low skew-low power clock.(Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Sreekanth, M.; Bhatt, AmitIn synchronous VLSI chips, clock distribution network plays an important role. The quality of clock network mainly effects the performance of the chip, because the speed of data transfer depends on clock signal. Achieving minimum clock latency and clock skew becomes difficult when we have clock signals in terms of 100MHz. in the clock network, skew is one of the major concerns because of this clock rate decreases. In this document, the main focus is on Clock Tree Synthesis (CTS) methodology for achieving low skew. Primarily CTS requires inputs like target skew, maximum delay, minimum delay. In this report we analyze the effect of these parameters on achieving low skew and low power clock. Then we will try to make a generalized conclusion to get low-skew and low power CTS. Due to on-chip variation, low power and design complexity, clock timing in diverging as technology shrinks down below 45 nm. As transistor goes below 45 nm technology, the timing gap becomes very severe as it reaches up to 50%. Clock Concurrent Optimization is a new approach which merger physical optimization into CTS and optimizes both clock delays and logic delays simultaneously. In this report we will discuss how CCOpt optimizes both logic and clock simultaneously. In addition to that we will discuss the key benefits of CCOpt when compared to CTS.Item Open Access Study of the effectiveness of various low power techniques on sequential and combinational gate dominated designs(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Rana, Kunj; Bhatt, AmitIn last decade, the technological advancement is seen in semiconductor field like never before. The need for low power has caused a major paradigm shift where power dissipation has become as important consideration as performance and area. The size of the electronic equipments is getting smaller and smaller which requires smaller integrated circuits (ICs). Due to this the power consumption happens to be a major concern in developing the smaller ICs. The objective of the dissertation is to develop a low power digital design flow using Cadence® tools. This report discusses various strategies and methods for designing low power circuits and systems. It describes the many issues facing designers at various levels and presents some of the techniques that have been proposed to overcome these difficulties. To do this, particular RTL (Verilog code) is taken for some design. First various floorplans are tested on the design for better power number then using the same design, analysis on two different interconnect estimation model is done. Finally using the floorplan and interconnect estimation model analysis results low power implementation is done for the same design which is passed through various steps of digital design flow like synthesis, floor planning, placement, routing, and converted to GDSII (Graphic Database System) file format which can be directly sent to foundry. In low power implementation several techniques like clock gating, operand isolation, and multi Vt cells are used with some enhancement switches provided by the toolItem Open Access Design of the high speed, high accuracy and low power current comparators(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Chasta, Neeraj Kumar; Parikh, Chetan D.Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”. A current comparator can be referred as trans-impedance amplifiers which compares applied input currents and generate CMOS compatible output voltage. In this work, study and simulations of various current domain comparator circuits have been done; some of these follow basic analog circuit concepts like current mirroring and Voltage current feedback. This thesis presents a novel idea for analog current comparison with controlled hysteresis. Proposed circuit is based on current mirror and latching techniques. Comparator presented is designed optimally in 0.18μm CMOS process in LTspice environment. Designing issues have also been discussed for no hysteresis (or very less hysteresis) case, where comparator gives higher accuracy and speed at the cost of increased power consumption. In addition to this a simple circuit is proposed which satisfies high speed, high accuracy and low power consumption constraints for the mentioned technology parameters. It utilizes amplification properties of Common gate circuit for generating CMOS compatible output voltage by comparison of applied input signal current and reference currentItem Open Access High speed sample and hold circuit design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dwivedi, Varun Kumar; Parikh, Chetan D.Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its front-end component. In this thesis, the high speed sample and hold circuit has been designed, requiring low power as a front end block of pipeline analog to digital converter. In this work, architectures of sample and hold circuit are studied and issues which limit the performance of sample and hold circuits are discussed. A fully differential S/H circuit using bottom plate sampling is proposed. The circuit has been designed in order to meet the specification. Amplifiers are studied and folded-cascode amplifier is chosen as an optimum architecture for switch capacitor based sample and hold circuit. The proposed circuit is designed optimally in a 180 nm CMOS process, in the Cadence Spectre environment. The speed and power achieved are 125 MSPS, 6.8mW respectively.Item Open Access Built-in self test architecture for mixed signal systems(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Jain, Mahavir Rajmal; Mandal, Sushanta; Nagchoudhuri, DipankarBuilt-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and used for digital circuitry due to well defied fault models and advanced designs tools and techniques available. But with more analog circuitry being built on same platform with digital circuitry, the necessity for BIST architecture of mixed signal system on chip is increasing. The proposed BIST scheme is developed to test the data converters, both DAC and ADC on chip as well as other analog IP modules depending on specification of design without/least affecting the architecture of actual design and without making use of any complex DSP circuitry. The concept of internet node access based testing of digital blocks is also used for dynamic parameter of DAC like offset voltage and gain error, monotonicity and linearity non-specific BIST scheme. Letter the digital control logic protion of SAR ADC is tested with scan-chain insertion and thus overall functionality of SRA ADC is verified. A simple comparison based method is also proposed for other type ADCs. For other anlog IPs, we propose IP-based testing where digital to analog converted test signals can be applied depending on specifications of IP design from vendor without affecting architecture of the design. The output from IPs are taken at different nodes and applied directly to ADC on chip. The digitized output response is then compared with expected response to test the functionality of the DUT and find out its deviation from desired value to achieve pre-defined level of accuracy. The design failing any of the sequence of afore-mentioned test is discarded faulty. The circuitry is designed and evaluated at schematic level using TSMC complementary metal oxide-semiconductor (CMOS) 0.5um technology.Item Open Access Analysis and modeling of power distribution network and decoupling network design strategies for high speed digital and analog VLSI system(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Pathak, Abhishek; Mandal, Sushanta; Nagpal, Raj Kumar; Nagchoudhuri, DipankarToday’s high speed digital and analog VLSI systems are operating in GHz frequency range. With high switching rate of the devices, power distribution network (PDN) impedance causes ripples in power supply. If PDN is not designed properly it can cause false switching, or even it can damage the device permanently. In this thesis whole power distribution network (PDN) for VLSI system has been modeled using RLC equivalent circuits which can be run on any simulation program with integrated circuit emphasis (SPICE) based simulator. Frequency dependent RLC model for printed circuit board (PCB) and package interconnects has been generated, and effects of different geometry and material of interconnects on PDN impedance profile have been analyzed. Model is compared with electromagnetic (EM) full wave simulator both for the accuracy and CPU run time and it is found that model shows good accuracy with very less CPU run time as compared to full wave simulator which can take more than a day to simulate whole geometry. To meet the target impedance of PDN, Strategies for choosing decoupling capacitors and their placement over power plane have been analyzed. Key-words: Power Integrity, power delivery network, voltage regulator, simultaneous switching noise.Item Open Access Low power SRAM design(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Bambhaniya, Prashant; Dubey, RahulIn the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power consumption has become an important factor. Battery operated portable devices which performing the high performance processing task also consumes lots of power. The various methodologies are used to reduce the power dissipation by optimizing the parameters that are related to power consumption of circuit. The Static RAM is used as a cache memory in the processor and also has an application in the embedded system. Due to continuous advances in the integrated circuit technology, the density of SRAMs in embedded application has grown substantially in recent years. The SRAM block is becoming indispensable block in the system-on-chips (SoCs). The larger density SRAM block has a highly capacitive bit lines and data lines. The dynamic power of SRAM is mainly due to charging and discharging of highly capacitive lines. To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will consumes a greater amount power according to law of CV2f. Thus voltage swing reduction is an effective way to decrease the power dissipation. The current mode sensing technique is proposed to give the small voltage swing on the bit lines during write operation. In the proposed method the layout and simulation is done for the one bit line pair for three different methodologies. The bit line interference of selected cell with adjacent selected and non selected cell is also checked out. The proposed current conveyor method has shown an improvement in terms power dissipation over the voltage write and current read (VWCR) and current write and current read (CWCR) method without comprising the performance.Item Open Access Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Ranjith, P; Nagchoudhuri, Dipankar; Mandal, Sushanta KumarThis thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. Different logic families have been studied and Complementary Pass-transistor Adiabatic Logic (CPAL) is chosen to implement an adiabatic carry save multiplier as it gives less energy dissipation per cycle than other logic families at higher load capacitances and higher loads. The power clock is designed for CPAL which requires four phase trapezoidal waveform. An 8-bit carry save multiplier is designed which is used as load to clock generation circuit. The clock generator consumes equal energy per cycle at all frequencies. The control logic required for clock generation circuit is also simple to implement. Conversion efficiency of the order of 10% is obtained for an equivalent load capacitance of 2pF. The simulations are done using LT spice in 0.25μm TSMC technology. Layouts are drawn in MAGIC 7.1.Item Open Access Design of low power and high speed decoder for 1MB memory(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Gupta, Punam Sen; Nagchoudhuri, DipankarTechnology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with minimum loss in speed and slightly overheads in terms of chip area. This circuit generates slightly lower supply voltage when the load circuitry is in the standby mode thereby raises the Vt of the CMOS transistors and hence reduces leakage power dissipation The overall power dissipation of a 7x128 decoder is reduced from 0.928mW to 0.584mW for 1Mb Memory with voltage controllable circuit, namely 37% lowering in power dissipation. The operating voltage for the design is 1.2 V. Layout is done in magic 7.1 version in 180nm technology. The simulations are done in LT spice.