M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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Now showing 1 - 6 of 6
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    Study of power in CR-SRAM in context of precharge reference voltage.
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Rupapara, Kripal D.; Zaveri, Mazad S
    In Morden times power dissipation in electronic circuits has become more important due to increase use of portable and handheld devices. Increased operating frequency results in more power consumption in almost every VLSI circuits. Scaling in integrated circuit technology directly paves way to increased package density, thereby increasing on chip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. Large fraction of power is consumed by memory circuits, if we can reduce power consumed by memory structure can reduce overall power consumption. This thesis is mainly concentrated on various components of power consumption in digital circuits, operation of SRAM, various technique to reduce power in SRAM and finally illustrates charge recycling SRAM for lower power consumption.
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    Novel 7T SRAM cell design for low power cache applications
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Joshi, Srawan Kumar; NagChoudhuri, Dipankar
    Scaling in integrated circuit technology directly paves way to increased package density, thereby increasing onchip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. SRAM is used as on chip cache memory. A major part of the power consumption in any memory architecture is due to charging and discharging of highly capacitive bitlines and wordlines. Existing techniques mainly concentrated on the reduction of power due to the capacitive bitlines and wordlines. In this thesis, a new 7T SRAM cell has been proposed with a single bitline architecture which reduces the dynamic power consumption to a great extent. This proposed design resulted in power reduction of write ‘0’ and read ‘0’ operation, based on the fact that the majority of the cache writes are 0’s. A memory array of size 256Kb (512x512) was designed using the basic 6T SRAM and propsed 7T SRAM cell to carry out the simulations and compare the results for power optimization. The simulations were done using Cadence Virtuoso (ADE) tool in gpdk180 library using 0.18μm technology. With the proposed SRAM cell implementing 256Kb memory array, reduction of write power (approximately 80%) and read power (approximately 55%) is achieved compared to conventional SRAM array. There is an area overhead of 28.76% using the present 180nm technology.
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    ItemOpen Access
    Column decoder for memory redundant cell array
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Nahar, Pinky; Nagchoudhuri, Dipankar
    As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy circuit to enhance the reliability for the faulty columns in memory array. The online testing circuit generates the signals for faulty columns, which enables the redundant circuit to replace faulty with spare column of cells. The redundant decoder and multiplexer provide the path to replace the faulty columns with the spare columns. The novel feature of proposed work is that, input of redundant column decoders depends upon the number of bits for a word output instead of the address signals. The proposed circuit provides the reliability with some loss in speed and overhead in terms of chip area. The operating voltage for the design is 3V. The layout and simulations are performed in CADENCE tool for .1μm technology. The performance parameters of various decoders are performed in LT Spice for .18μm technology.
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    Design of row decoder for redundant memory cell (SRAM)
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Mishra, Ashwini Kumar; Nagchoudhuri, Dipankar
    In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory array. The proposed circuit increases the yield and reliability with some loss in speed and overhead in terms of chip area. The circuit designed can test the design whenever a command to test is issued and it will detect and store the faults. Control Circuit designed, checks whether the given address of the memory operation is correct or not. If the address is faulty it replaces the faulty address with the spare address available in the chip. The existing control mechanism to replace faulty cell in a row replaces the cell bit by bit. But the design here instead of replacing the bit wise cells replaces the entire row containing the faulty cell. This architecture is more useful when there are more faulty cells in a single row. The row decoder is optimally implemented to reduce the time to access the data from memory. The operating voltage for the design is 3V. Layout, Simulation of testing circuit and redundant circuit with row decoder has been designed in CADENCE tool for .18μm technology. This Row decoder is working with 2.5GHz frequency.
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    ItemOpen Access
    Low power SRAM design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Bambhaniya, Prashant; Dubey, Rahul
    In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power consumption has become an important factor. Battery operated portable devices which performing the high performance processing task also consumes lots of power. The various methodologies are used to reduce the power dissipation by optimizing the parameters that are related to power consumption of circuit. The Static RAM is used as a cache memory in the processor and also has an application in the embedded system. Due to continuous advances in the integrated circuit technology, the density of SRAMs in embedded application has grown substantially in recent years. The SRAM block is becoming indispensable block in the system-on-chips (SoCs). The larger density SRAM block has a highly capacitive bit lines and data lines. The dynamic power of SRAM is mainly due to charging and discharging of highly capacitive lines. To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will consumes a greater amount power according to law of CV2f. Thus voltage swing reduction is an effective way to decrease the power dissipation. The current mode sensing technique is proposed to give the small voltage swing on the bit lines during write operation. In the proposed method the layout and simulation is done for the one bit line pair for three different methodologies. The bit line interference of selected cell with adjacent selected and non selected cell is also checked out. The proposed current conveyor method has shown an improvement in terms power dissipation over the voltage write and current read (VWCR) and current write and current read (CWCR) method without comprising the performance.
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    ItemOpen Access
    Design of a high speed I/O buffer
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Rathore, Akhil; Parikh, Chetan D.
    In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. CML buffers achieves high speed due to low output voltage swing which reduces transition time. Presently CML buffers are designed with differential architecture and uses different bandwidth extension technique (inductive peaking, negative miller capacitance, active feedback) to increase the speed. At high frequency, input output coupling limits the bandwidth due to miller effect because of gate to drain capacitance. The proposed design incorporates the architecture which reduces miller effect, hence achieves high bandwidth. In this topology a source follower drives a common-gate stage which is an example of ‘unilateral’ amplifier, that is, one in which signal can flow only in one way over large bandwidths. It reduces unintended and undesired feedback. This CML buffer is designed for OC-192/STM-64 application to be used in limiting amplifier which is a critical block in optical system. OC-192/STM-64 works around 10Gbps.