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  4. Column decoder for memory redundant cell array

Column decoder for memory redundant cell array

Files

200811026.pdf (814.77 KB)

Date

2010

Authors

Nahar, Pinky

Journal Title

Journal ISSN

Volume Title

Publisher

Dhirubhai Ambani Institute of Information and Communication Technology

Abstract

As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy circuit to enhance the reliability for the faulty columns in memory array. The online testing circuit generates the signals for faulty columns, which enables the redundant circuit to replace faulty with spare column of cells. The redundant decoder and multiplexer provide the path to replace the faulty columns with the spare columns. The novel feature of proposed work is that, input of redundant column decoders depends upon the number of bits for a word output instead of the address signals. The proposed circuit provides the reliability with some loss in speed and overhead in terms of chip area. The operating voltage for the design is 3V. The layout and simulations are performed in CADENCE tool for .1μm technology. The performance parameters of various decoders are performed in LT Spice for .18μm technology.

Description

Keywords

Electronic circuit design, Integrated circuits, Fault tolerance, Integrated circuits, Design and construction, Metal oxide semiconductors complementary, Design, Random access memory, Simulation, Redundancy techniques

Citation

Nahar, Pinky (2010). Column decoder for memory redundant cell array. Dhirubhai Ambani Institute of Information and Communication Technology, x, 45 p. (Acc.No: T00261)

URI

http://ir.daiict.ac.in/handle/123456789/298

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