M Tech Dissertations
Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3
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Item Open Access Design of the high speed, high accuracy and low power current comparators(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Chasta, Neeraj Kumar; Parikh, Chetan D.Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”. A current comparator can be referred as trans-impedance amplifiers which compares applied input currents and generate CMOS compatible output voltage. In this work, study and simulations of various current domain comparator circuits have been done; some of these follow basic analog circuit concepts like current mirroring and Voltage current feedback. This thesis presents a novel idea for analog current comparison with controlled hysteresis. Proposed circuit is based on current mirror and latching techniques. Comparator presented is designed optimally in 0.18μm CMOS process in LTspice environment. Designing issues have also been discussed for no hysteresis (or very less hysteresis) case, where comparator gives higher accuracy and speed at the cost of increased power consumption. In addition to this a simple circuit is proposed which satisfies high speed, high accuracy and low power consumption constraints for the mentioned technology parameters. It utilizes amplification properties of Common gate circuit for generating CMOS compatible output voltage by comparison of applied input signal current and reference currentItem Open Access Column decoder for memory redundant cell array(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Nahar, Pinky; Nagchoudhuri, DipankarAs the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy circuit to enhance the reliability for the faulty columns in memory array. The online testing circuit generates the signals for faulty columns, which enables the redundant circuit to replace faulty with spare column of cells. The redundant decoder and multiplexer provide the path to replace the faulty columns with the spare columns. The novel feature of proposed work is that, input of redundant column decoders depends upon the number of bits for a word output instead of the address signals. The proposed circuit provides the reliability with some loss in speed and overhead in terms of chip area. The operating voltage for the design is 3V. The layout and simulations are performed in CADENCE tool for .1μm technology. The performance parameters of various decoders are performed in LT Spice for .18μm technology.Item Open Access 1v rail to tail operational amplifier design for sample and hold circuits(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Kumar, Mahesh; Parikh, Chetan D.At low voltage, the input common mode voltage of Operational amplifier is limited which restricts its use as a buffer. This works deals with designing a rail to rail amplifier. The Thesis presents a 1V rail to rail operational amplifier that has been used as a unity gain buffer in the sample and hold circuit for 1V 10 bit 1MSPS pipeline ADC in 0.18?m technology. The Operational amplifier is designed using dynamic level shifting technique which uses an additional input CM adapter circuit for fixing the input common mode voltage. Novelty in the input CM adapter circuit and a low value of gm fluctuation (�0.245%) has been achieved. The Operational amplifier is implemented in standard CMOS technology. An open loop architecture is chosen for the implementation of sample and hold circuit. The transmission gate switch is used in the sample and hold circuit for reducing the effect of channel charge injection and clock feedthrough. Also, the transmission gate switch offers a low resistance as compared to pMOS or nMOS switches. The sample and hold circuit speed up to 1MSPS has been achieved.Item Open Access Design issues in direct conversion receiver(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Gupta, Amit Kumar; Gupta, SanjeevThe wireless system is being rapidly proliferated in our life. The growing of capacity in wireless communication requires a new type of wireless communication method which does not affect current work on circuits and systems that can operate on gigahertz wide signals will undoubtedly be the wave of the future as pressures to supply multimedia services over wireless continue to build. To achieve the goal of single receiver which can act on various different standards the Direct Conversion Receiver (DCR) is the most suitable architecture. The DCR has been known for quite long years. There are number of design issues related to the implementation of DCR. This thesis presents the issues which are related to design of Direct Conversion along with the design issues related to LNA design.Item Open Access Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Ranjith, P; Nagchoudhuri, Dipankar; Mandal, Sushanta KumarThis thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. Different logic families have been studied and Complementary Pass-transistor Adiabatic Logic (CPAL) is chosen to implement an adiabatic carry save multiplier as it gives less energy dissipation per cycle than other logic families at higher load capacitances and higher loads. The power clock is designed for CPAL which requires four phase trapezoidal waveform. An 8-bit carry save multiplier is designed which is used as load to clock generation circuit. The clock generator consumes equal energy per cycle at all frequencies. The control logic required for clock generation circuit is also simple to implement. Conversion efficiency of the order of 10% is obtained for an equivalent load capacitance of 2pF. The simulations are done using LT spice in 0.25μm TSMC technology. Layouts are drawn in MAGIC 7.1.Item Open Access Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sesha Sai, Aduru Venkata Raghava; Parikh, Chetan D.In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor using a low-voltage gyrator topology with a feedback resistance, where feedback resistance is realized by a NMOS operating in triode region whose bias voltage tunes the inductance of the active inductor and hence the frequency of VCO. The simulation results shows that this VCO operates in a 1.19 GHz to 2.49 GHz , while consuming 1.09 mW from a 1.2V power supply. The VCO’s phase noise level is -86.9 dBc/Hz at 1 MHz offset from a 1.55 GHz carrier. The deviation of the phase noise is 11.5 dBc/Hz during this tuning range. All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology.