Person: Bhatt, Amit
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Amit Bhatt
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Publication Metadata only 32 bit RISC pipelined processor(01-02-2005) Bhatt, Amit; Sachdeva, Charu; Desai, Meghana; Chaudhary, Niket; Chousksey, Siddarth; Bansal, Yogesh; Ahmed, Taukheer; Abbasi, Taher; Bhatt, Amit; Bhatt, Amit; Bhatt, Amit; Bhatt, Amit; Bhatt, Amit; DA-IICT, Gandhinagar; Sachdeva, Charu (200101145); Chaudhary, Niket (200101116); Bansal, Yogesh (200101104)The main goal of this study is to develop a 32-bit pipelined processor with several clock domains based on the RISC-V (open source RV32I Version 2.0) ISA. To minimise the complexity of the instruction set and speed up the execution time per instruction, RISC (Reduced Instruction Set Computer) is a type of processor that uses less hardware than CISC (Complex Instruction Set Computer) is used. Furthermore, we constructed this processor with five levels of pipelining, resulting in parallelism in instruction execution. With the aid of necessary block diagrams, all of the processes are well described. Multiple clock domains employing two clock sources are used to ensure that variable delays such as clock skew and metastability are avoided within the stage pipeline registers. Quartus Prime was used to design and synthesis this processor, which was written in Verilog HDL. ModelSim was used to verify this design, and all of the instructions have been thoroughly checked. Furthur the processor is implemented on the �ALTERA Cyclone 10 LP� board for calculating the device utilization.Publication Metadata only Performance prediction from simulation systems to physical systems using machine learning with transfer learning and scaling(Wiley, 15-08-2023) Mankodi, Amit; Bhatt, Amit; Chaudhury, Bhaskar; DA-IICT, GandhinagarSelection from several computer systems with different hardware features resulting in different software performance is a critical problem to solve. The problem becomes even more challenging when access to computer systems with different features is difficult. We had proposed a novel solution, �cross performance prediction with scaling,� in our previous work. In the scaling model, we predicted the physical system's runtime using a machine learning model trained only on a performance dataset of simulation-based systems applying a scaling factor to the predicted runtime. In this article, we propose another novel idea, �cross performance prediction with transfer learning,� that uses transfer learning to solve the same problem. This model predicts the target physical system's performance using a machine learning model trained on a combined performance dataset from simulation-based systems and an accessible source physical system. We evaluate both the models using several benchmark algorithms from SD-VBS and MiBench suites. Our scaling model results have achieved a prediction error of 10%�25% for general-purpose systems, whereas the transfer learning model has higher errors in the range of 50%. We have also developed a method to extract the rules built during the decision tree model's training to predict the runtime.Publication Metadata only Predicting physical computer systems performance and power from simulation systems using machine learning model(Springer, 01-05-2023) Mankodi, Amit; Bhatt, Amit; Chaudhury, Bhaskar; DA-IICT, GandhinagarThis paper summarizes the background and motivation behind the�Let�s HPC�project, the design philosophy of the platform, the present capabilities of the platform, as well as the plans for future developments.