32 bit RISC pipelined processor

Abstract

The main goal of this study is to develop a 32-bit pipelined processor with several clock domains based on the RISC-V (open source RV32I Version 2.0) ISA. To minimise the complexity of the instruction set and speed up the execution time per instruction, RISC (Reduced Instruction Set Computer) is a type of processor that uses less hardware than CISC (Complex Instruction Set Computer) is used. Furthermore, we constructed this processor with five levels of pipelining, resulting in parallelism in instruction execution. With the aid of necessary block diagrams, all of the processes are well described. Multiple clock domains employing two clock sources are used to ensure that variable delays such as clock skew and metastability are avoided within the stage pipeline registers. Quartus Prime was used to design and synthesis this processor, which was written in Verilog HDL. ModelSim was used to verify this design, and all of the instructions have been thoroughly checked. Furthur the processor is implemented on the �ALTERA Cyclone 10 LP� board for calculating the device utilization.