Person:
Agrawal, Yash

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Yash Agrawal

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Faculty

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079-68261629

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VLSI, Nanotechnology, Numerical Method Techniques--FDTD, Design Techniques and Modelling Schemes of High-speed on-chip VLSI Interconnects, Modeling and Simulation Schemes, Advanced Devices and Their Modeling, Analysis

Abstract

Biography

Dr. Yash Agrawal received his Ph.D. and M.Tech. Degrees in VLSI Design Automation and Techniques in E&CE Department from National Institute of Technology, Hamirpur, Himachal Pradesh, India. Dr. Yash has been expert and distinguished guest at various places. He is Editor and Reviewer of several reputed Journals. He has been Secretary and Coordiantor of various forums and events. He has organized several workshops and part of the organizing committee in various Trainings, Seminars, and Conferences. He has been the Chairman and awarded with best forum member of IETE Forum at KITS Ramtek, Nagpur Division during 2008-2009. He has been awarded with prestigious IETE—K S Krishnan Memorial Award-2017 for the Best System Oriented research paper. He achieved third place in All India Mentor Graphics design contest held at Bangalore, India in 2011. He has received 2nd Runner up and Cash Prize of Rs. 50,000/- in All India Mentor Graphics Design Contest held at Bangalore. He has several publications in Book Chapters of Springer, Journals including IEEE Transactions in Electromagnetic Compatibility, Nanotechnology, Springer, Taylor and Francis and several national and international reputed Conferences.

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2016 - 201982020 - 202520

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Search Results

Now showing 1 - 10 of 29
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    In-House Developed Graphene-Based Leaf Wetness Sensor With Enhanced Stability
    (IEEE, 01-06-2025) Patle, Kamlesh; Yogi, Pooja; Maru, Devkaran; Palaparthy, Vinay; Moez, Kambiz; Agrawal, Yash; DA-IICT, Gandhinagar
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    Essential Frequency Analysis for Stacked Cu-CNT Composite Cells of TSVs
    (IEEE, 04-03-2025) Kumar, Mekala Girish; Agrawal, Yash; Pulluri, Harish; Sharma, Rohit; DA-IICT, Gandhinagar
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    Reliability Assessment using Electrical and Mechanical Characterization of Stretchable Interconnects on Ultrathin Elastomer for Emerging Flexible Electronics System
    (IEEE, 10-07-2025) Bhatti, Gulafsha; Sharma, Rohit; Kumar, Mekala Girish; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, Gandhinagar
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    An Efficient Crosstalk Model For Coupled Multiwalled Carbon Nanotube Interconnects
    (IEEE, 01-04-2018) Kumar, Mekala Girish; Chandel, Rajeevan; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; DA-IICT, Gandhinagar
    In this paper, the crosstalk effects in coupled multiwalled carbon nanotube (MWCNT) interconnects have been analyzed. An unconditionally stable finite-difference time-domain (USFDTD) technique has been used for the crosstalk model. The in_phase delay, out_phase delay, and crosstalk noise for coupled interconnect lines have been determined. It is observed that crosstalk effect is less severe in MWCNT interconnects compared to the conventional copper interconnects. The results of the proposed model have been verified with the conventional FDTD technique, hailey simulation program with integrated circuit emphasis (HSPICE), and feature selective validation. For transient analysis, the proposed model on an average consumes 46% lesser CPU runtime as compared to the conventional FDTD technique. Further, stress and electro-migration effects have been analyzed for copper and MWCNT interconnects. The mean time to failure of MWCNT interconnects is found to be superior than that of copper interconnects.
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    Carbon Nanotube Interconnects - A Promising Solution for VLSI Circuits
    (Taylor & Francis, 26-04-2016) Kumar, Mekala Girish; Agrawal, Yash; Chandel, Rajeevan; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; DA-IICT, Gandhinagar
    In nanoscale regime, the performance of traditional copper interconnects degrades substantially in terms of latency, power dissipation and induced crosstalk noise. This is due to miniaturization of electronic devices and many-fold enhancement of interconnect lengths in very large-scale integrated (VLSI) circuits. However, carbon nanotubes (CNTs) due to their unique physical properties such as high thermal conductivity, current carrying capability and mechanical strength have drawn the attention of researchers in recent times. The present paper provides comprehensive investigations in the various CNT structures for on-chip VLSI interconnect applications. Different configurations of CNT structures are studied namely single-wall CNT (SWCNT), multiwall CNT (MWCNT) and mixed-wall CNT bundle (MCB). The performance of CNT interconnects is analyzed using driver-interconnect-load system. It is investigated that the reduction in propagation delay in MCB interconnect is nearly 69%, 60%, 40% and 22% as compared to copper, SWCNT bundle, MWCNT and MWCNT bundle interconnect structures, respectively. This analysis considers an interconnect length variation from 500 to 2500 �m for 32-nm technology node. For the same dimensions the overall reduction in power dissipation in MCB interconnect is nearly 60%, 49%, 45% and 36% as compared to copper, SWCNT, MWCNT and MWCNT bundle interconnects, respectively. Furthermore, the effect of crosstalk on the interconnect structures has been examined. It is investigated that MCB has least crosstalk induced delay than all the other interconnect structures. Consequently, it is envisaged that MCB outperforms copper, SWCNT, MWCNT and MWCNT bundle interconnects and are best suited for future VLSI interconnects.
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    Experimental Investigation of Leaf Wetness Sensing Properties of MoS2 Nanoflowers-Based Flexible Leaf Wetness Sensor
    (IEEE, 01-02-2023) Khaparde, Priyanka; Patle, Kamlesh S; Agrawal, Yash; Borkar, Hitesh; Palaparthy, Vinay; Gangwar, Jitendra; Roy, Anil; Agrawal, Yash; Palaparthy, Vinay; Roy, Anil; Patle, Kamlesh S (202121017)
    To abate crop loss, it is important to explore the plant disease management systems, where leaf wetness sensors (LWS) are widely used. The leaf wetness duration (LWD) extracted from the LWS is related to plant diseases. In this work, we have fabricated the LWS on the polyamide flexible substrate where Molybdenum disulfide (MoS2) is used as the sensing film to explore the leaf wetness sensing mechanism. Further, we have passivated the MoS2�with the help of acrylic protective lacquer (APL) conformal coating (MoS2�+ APL), which reduce the interaction of the water molecules with the sensor. Lab measurements indicated that fabricated LWS on the flexible substrate with MoS2�and MoS2�+ APL as the sensing film offers a response of about ? 40 000% and ? 250%, respectively, at 500 Hz excitation frequency when the entire sensing area is filled with the water molecule. The response time of the MoS2�and APL-coated flexible sensor is about 180 s. Fabricated LWS sensors offer hysteresis of about � 4% in wetness. Further, we have identified that oxidation of the sulphur in the MoS2�plays an important role in the leaf wetness sensing mechanism. Furthermore, we understood that MoS2�when passivated with APL coating, the oxidation effect is reduced and the sensor response is negligible.
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    Impact of Electrode Patterns Variation on the Response Characteristic of Leaf Wetness Sensors
    (IEEE, 05-08-2024) Patle, Kamlesh S; Sharma, Neha; Khaparde, Priyanka; Varshney, Harsh; Bhatti, Gulafsha; Agrawal, Yash; Palaparthy, Vinay; DA-IICT, Gandhinagar; Patle, Kamlesh S(202121017); Sharma, Neha (202211051); Varshney, Harsh (202211001); Bhatti, Gulafsha (202021005)
    Prediction of plant diseases is essential to reduce crop loss. Early disease prediction models have been investigated for this purpose, where data on leaf wetness duration (LWD) is one of the key components. Leaf wetness sensors (LWSs) are used to better understand how foliar wetness affects plant disease cycles and epidemic development. LWS can be fabricated on printed circuit boards (PCBs), where interdigitated electrode patterns are widely used. However, it is important to understand the efficacy of these patterns for in-situ measurements. For this purpose, in this work, we have fabricated three different patterns viz. circular, oval, and rectangular on the PCB and tested their efficacy during lab and field measurements. Lab measurements indicate that the circular patterned LWS offers a sensitivity of about 1600% over the dry-to-wet range, which is about 2 and 1.5 times more than oval and rectangular patterns, respectively. Besides this, circular patterned LWS offers the hysteresis of about 2%, whereas the oval and rectangular patterned LWS show about 3% and 7%, respectively. Field measurement results specify that circular patterned LWS and commercial LWS Phytos 31 indicate the same number of LWD events. However, oval and rectangular patterned LWS shows extra false events.
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    A Literature Review on Next Generation Graphene Interconnects
    (World Scientific, 01-11-2018) Patel, Nikita; Agrawal, Yash; DA-IICT, Gandhinagar; Patel, Nikita (201421003)
    The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented.
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    A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects
    (Elsevier, 01-12-2021) Kumar, Mekala Girish; Agrawal, Yash; Vobulapuram Kumar, Ramesh; Chandel, Rajeevan; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; DA-IICT, Gandhinagar
    With the feasibility to scale the devices and interconnects in highly sophisticated VLSI technology, the demand for high-speed and low-power�e-applications have also subsequently increased stupendously. Based on the applications and requirements, a VLSI system is operated in different modes as linear or sub-threshold. A unified analytical model for describing both these linear and sub-threshold modes is highly desirable. This has been innovatively presented in the current paper. Moreover, the futuristic and emerging mixed�carbon nanotube�bundle (MCB) as interconnects for both linear and sub-threshold region of operations has been considered. The essential signal integrity analysis comprising of several�crosstalk�effects such as associated�transient response, delay and power have been analyzed. To evaluate this, analytical model is formulated and proposed using accurate unconditionally-stable finite-difference time-domain (USFDTD) technique. Utilizing the proposed model, it is investigated that linear mode of operation is good for realizing high-speed systems while sub-threshold is a preferable operation for applications targeted for low-power. Comprehensively, it is envisaged that the average power-delay-product in MCB interconnects operating in sub-threshold region is low and reduced by 74% compared to corresponding linear region of operation. Also, it is demonstrated that the proposed unified USFDTD based model for MCB interconnects operating in different modes of operation is stable and not constricted by the Courant condition. At maximum allowable�time step, the proposed model is nearly 10 and 25 times faster than the conventional FDTD analytical and HSPICE simulation models, respectively. The results reveal that USFDTD technique provides better accuracy than the FDTD technique. The different performance analyses are performed at 22�nm technology node.
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    A Novel Unified Model for Copper and MLGNR Interconnects using Voltage and Current-Mode Signaling Schemes
    (IEEE, 01-02-2017) Agrawal, Yash; Kumar, Girish; Kumar, Mekala; Chandel, Rajeevan; DA-IICT, Gandhinagar
    A novel unified model, for conventional copper and futuristic multilayer graphene nanoribbon (MLGNR) interconnects, based on a finite-difference time-domain (FDTD) technique has been proposed in this paper. The performance of quasi-transverse electromagnetic model of interconnects has been exhaustively analyzed for both voltage-mode signaling (VMS) and current-mode signaling (CMS) schemes. The effect of variations in edge roughness and dopant dependent Fermi energy in MLGNR interconnects has been examined. The crosstalk and coupling effects in interconnects have been investigated by incorporating capacitive and inductive interconnect parasitic elements. From the results carried out for 32-nm technology node, it has been observed that for similar dimensions and operating conditions, MLGNR interconnects show a significant performance improvement over the copper interconnects. The results also show that the CMS scheme outperforms VMS scheme at global wire lengths and is very suitable for state-of-the-art chip applications. The proposed model results are in close propinquity with the SPICE results. Furthermore, the FDTD-based model is computationally efficient compared to SPICE.