Theses and Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/1

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    Adaptive analog line driver using digital tuning
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Singh, Harsh Verdhan; Sen, Subhajit
    Transmission lines are widely used for transmitting electrical signals. A line driver is a part of the analog front-end transmitter for wired line communication. It is a voltage buffer that provides the necessary output current to drive the small load impedance of a terminated transmission line. The adaptive line driver must adapt to the load impedance of a terminated transmission line for minimizing reflections. The main requirements of an adaptive line driver are good matching to the input impedance of the transmission line over process variations, high output swing, unity gain. Existing adaptive line drivers use analog tuning methods for adapting to the load impedance. This thesis proposes a new technique for tuning output impedance of the line driver. A digital tuning method is used to correct the output impedance of the line driver to match with the input impedance of the transmission line. The aim of using the digital tuning method is to achieve better tuning range over existing analog tuning methods. The tuning scheme uses a comparator followed by counter and current DAC(digital- to-analog converter). A comparator is used for comparing input and output signal of line driver and generates control signal which is applied to a counter that controls the current DAC. This feedback loop ensures unity gain between the input and out- put voltages and thereby ensures tuning of the output impedance of the line driver. The analog line driver is implemented in GPDK-180nm technology and simulated in Cadence Virtuoso Environment.
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    Bidding strategies for dynamic spectrum allocation
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dhumal, Neha; Srivastava, Sanjay
    Dynamic Spectrum Allocation is the process of assigning spectrum licenses in terms of the chunks of the spectrum band to the Wireless Service Providers (WSPs). This allocation assignment is being done as per the WSPs' requirement and this in turn would depend on the end users' applications demand [16]. For Dynamic Spectrum Access, economic framework is needed to make the system feasible under economic terms. This process uses some kind of service pricing mechanism that the service provider can use for the acquisition of the spectrum band and requirement of the end users.

    In the Dynamic Spectrum Allocation scenario, the problem is to find the appropriate bidding strategies. The approach to this problem is to simulate the different cases with varying parameters. Here, the interaction between the spectrum owner and providers is modeled through auction model which has been studied in this work whereas the interaction between the providers and end users is based on the demand. This thesis presents the bidding strategies and appropriate prediction method that maximize the revenue and the profit of both the providers as well as the end users. The auction method and different bidding strategies adopted, gives the winning criteria for the providers on how many number of units to bid and the prices for these units. Prediction method for the price uses the concept of probability of winning the particular unit. Simulation results show the comparison between prediction and actual values, revenue and profits of the providers. Among the different auction and bidding methods, the Vickrey auction has been used in this work. In the Vickrey auction method, the allocation of the resources is done efficiently as compared to other methods and does provide dominant bidding strategy.

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    Investigation on multi-band fractal antennas for satellite applications
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Shah, Milind; Gupta, Sanjeev
    Remote sensing is a very important application of satellite communication. In remote sensing applications, multiple frequencies are utilized. Use of different antennas for different frequencies is a complex task and so use of single multiband antenna is desirable. Fractal geometries can be utilized to design single multiband antenna operating at various required frequencies which may be widely separated and non-harmonically related. In this thesis fractal geometry concept has been utilized to achieve multiband and compact design. Here multifractal cantor geometry is used due to its simple construction and ease in tuning. In addition to multiband behavior, the antenna must provide sufficient bandwidth. Unfortunately the microstrip antennas are having very narrow bandwidth. There are other techniques to increase bandwidth such as aperture coupled structure or electromagnetically coupled structure. But these solutions result in the complex multilayer structure. To prevent this complexity and to increase bandwidth, monopole structure has been utilized. Usually for satellite communication 28 dB to 32 dB gain is required. To fulfill this requirement, an array using multiband element is also designed.
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    Transaction based verification of discrete wavelet transform IP core using wishbone transactor
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Patel, Birenkumar; Dubey, Rahul
    Verification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debug at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. It does not require detailed test benches with large vector. Device under test (DUT) operates at a binary stimulus level(e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level (e.g. READ) and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The Discrete Wavelet Transform’s (DWT) Intellectual Property (IP) core is used as a DUT. DWT is implemented by Lifting scheme based Daubechies 9/7 filter. Lifting scheme has an advantage over conventional convolution method like time complexity of operation. Wishbone transactor is designed for verification of IP core. Whole system is verified on ZeBu emulator. The same Wishbone transactor is used for verification of different Wishbone compatible IP core.
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    Test methodology for prediction of analog performance parameters
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Akula, Sandeep; Nagchoudhuri, Dipankar
    Analog testing, the name itself signifies the detection of faults in analog circuits. The aim of this thesis is to increase the test effectiveness and work in the performance parameter space. There are many test methodologies which can detect the faults in the circuit under test (CUT), out of which the test methodologies which can determine CUT performance parameters resulting in enhanced test effectiveness are, predictive oscillation based test methodologies. To detect the catastrophic and parametric faults these methodologies are used. These test methodologies are preferred over other methodologies because the input test stimulus generation is not needed, which reduces the complexity if multiple inputs are applied to the circuit. These test techniques are implemented with prediction process using neural networks which will in turn increases the performance of the circuit under test. The thesis follows with the implementation of the techniques and understanding the methods to increase the test effectiveness. The design process is performed in CADENCE simulation tool with 180nm technology.
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    Built-in self test architecture for mixed signal systems
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Jain, Mahavir Rajmal; Mandal, Sushanta; Nagchoudhuri, Dipankar
    Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and used for digital circuitry due to well defied fault models and advanced designs tools and techniques available. But with more analog circuitry being built on same platform with digital circuitry, the necessity for BIST architecture of mixed signal system on chip is increasing. The proposed BIST scheme is developed to test the data converters, both DAC and ADC on chip as well as other analog IP modules depending on specification of design without/least affecting the architecture of actual design and without making use of any complex DSP circuitry. The concept of internet node access based testing of digital blocks is also used for dynamic parameter of DAC like offset voltage and gain error, monotonicity and linearity non-specific BIST scheme. Letter the digital control logic protion of SAR ADC is tested with scan-chain insertion and thus overall functionality of SRA ADC is verified. A simple comparison based method is also proposed for other type ADCs. For other anlog IPs, we propose IP-based testing where digital to analog converted test signals can be applied depending on specifications of IP design from vendor without affecting architecture of the design. The output from IPs are taken at different nodes and applied directly to ADC on chip. The digitized output response is then compared with expected response to test the functionality of the DUT and find out its deviation from desired value to achieve pre-defined level of accuracy. The design failing any of the sequence of afore-mentioned test is discarded faulty. The circuitry is designed and evaluated at schematic level using TSMC complementary metal oxide-semiconductor (CMOS) 0.5um technology.
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    Design of CDMA transmitter and three finger rake receiver
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Pateriya, Bhavana; Dubey, Rahul
    As cellular wireless communication becomes a worldwide communication standard, it is important in studying how data communications happens in a cellular system. In this Thesis work CDMA transmitter and receiver have been designed including the communication channel which include effects of multipath fading and noise. Effectiveness of rake receiver have been verified for varying SNR and with varying the number of fingers. Also the functionality of each block is analyzed.
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    Efficient ASIC implementation of advanced encryption standard
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Joshi, Ashwini Kumar; Nagchoudhuri, Dipankar
    In spite of the many defense techniques, software vulnerabilities like buffer overflow, format string vulnerability and integer vulnerability is still exploited by attackers. These software vulnerabilities arise due to programming mistakes which allows security bugs to be exploited. Buffer overflow occurs when buffer is given more data than the capacity of it. Format string vulnerability arises when data supplied by attacker is passed to formatting functions as format string argument. Integer vulnerability occurs when program evaluates an integer to unexpected value due to integer overflows, underflows, truncation errors or signed conversion errors. The hardware based solution called tagged architecture protects a system against mentioned vulnerabilities. In tagged architecture, each memory byte is appended with one tag bit to mark data that comes from I/O. Whenever I/O supplied data is used to transfer control of a system or to access memory, an alert is raised and program is terminated. This thesis proposes a weakness of tagged architecture by finding false positives and false negatives on it. It also proposes the improvements to the tagged architecture to avoid found false positives on it. The prototype implementation of improved tagged architecture is done in SimpleScalar simulator. The SimpleScalar simulator is a architectural simulator. The security evaluation is done for tagged architecture and improved tagged architecture through benchmarks and synthetic vulnerable programs.
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    Low power SRAM design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Bambhaniya, Prashant; Dubey, Rahul
    In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power consumption has become an important factor. Battery operated portable devices which performing the high performance processing task also consumes lots of power. The various methodologies are used to reduce the power dissipation by optimizing the parameters that are related to power consumption of circuit. The Static RAM is used as a cache memory in the processor and also has an application in the embedded system. Due to continuous advances in the integrated circuit technology, the density of SRAMs in embedded application has grown substantially in recent years. The SRAM block is becoming indispensable block in the system-on-chips (SoCs). The larger density SRAM block has a highly capacitive bit lines and data lines. The dynamic power of SRAM is mainly due to charging and discharging of highly capacitive lines. To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will consumes a greater amount power according to law of CV2f. Thus voltage swing reduction is an effective way to decrease the power dissipation. The current mode sensing technique is proposed to give the small voltage swing on the bit lines during write operation. In the proposed method the layout and simulation is done for the one bit line pair for three different methodologies. The bit line interference of selected cell with adjacent selected and non selected cell is also checked out. The proposed current conveyor method has shown an improvement in terms power dissipation over the voltage write and current read (VWCR) and current write and current read (CWCR) method without comprising the performance.
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    Improvement of tagged architecture for preventing software vulnerabilities
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Shah, Tejaskumar; Mathuria, Anish M.
    In spite of the many defense techniques, software vulnerabilities like buffer overflow, format string vulnerability and integer vulnerability is still exploited by attackers. These software vulnerabilities arise due to programming mistakes which allows security bugs to be exploited. Buffer overflow occurs when buffer is given more data than the capacity of it. Format string vulnerability arises when data supplied by attacker is passed to formatting functions as format string argument. Integer vulnerability occurs when program evaluates an integer to unexpected value due to integer overflows, underflows, truncation errors or signed conversion errors. The hardware based solution called tagged architecture protects a system against mentioned vulnerabilities. In tagged architecture, each memory byte is appended with one tag bit to mark data that comes from I/O. Whenever I/O supplied data is used to transfer control of a system or to access memory, an alert is raised and program is terminated. This thesis proposes a weakness of tagged architecture by finding false positives and false negatives on it. It also proposes the improvements to the tagged architecture to avoid found false positives on it. The prototype implementation of improved tagged architecture is done in SimpleScalar simulator. The SimpleScalar simulator is a architectural simulator. The security evaluation is done for tagged architecture and improved tagged architecture through benchmarks and synthetic vulnerable programs.