Theses and Dissertations

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    Energy Efficient Data Gathering In Wireless Sensor Network
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2017) Doshi, Digant Dilip; Pillutla, Laxminarayana
    "Energy consumption in Wireless Sensor Network(WSN) is one of the critical aspect that we try to look upon. In WSN we see the major energy dissipation is on the micro sensor, which is the core part of WSN. These Micro Sensor nodes with the non-chargeable and non-replaceable limited battery power will dry out very early as they keep on sensing the physical phenomenon, which will affect the network lifetime. In this work, we have introduced one data gathering approach named as Cooperative multiple-input multiple-output(MIMO). This will enhance the data gathering in WSN at a lower energy dissipation. We have also implemented some of the existing approaches to compare it with the our own proposed approach. We are not replacing or suggesting the whole new approach but we are just trying to modify the data gathering process in WSN such that it can result in very less energy consumption. In the proposed approach we look to the prospective of the local transmission between any two nodes which combinedly send the data to the next hop. Where in existing approaches we try to look for the minimum route and send to that route. We are trying here data compression also to reduce the number of bits travelling through the network just to minimize the traffic and also to minimize the energy. The results we got is quite a comparable to the existing approach and also the scenario we assumed for the comparison is exactly opposite of the proposed approach and in that particular scenario also, it gives a measurable results which can be further improved by adding some of the relatable scenarios."
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    Reconfigurable Interrupt Driven Low Power Processor Having Deterministic Response
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2017) Bhatnagar, Harshit; Bhatt, Amit
    "With the growth in number of portable devices and applications in variety,the computational complexities have increased many folds. With such increase in complexities, the computational requirement has also gone up. And the combination of computational complexities and requirements lead to high power consumption. In such a day and time of ever developing applications, we need a system that has the ability to achieve the computational complexity with lowest power possible. Hence we propose a system where a deterministic response is guaranteed along with the total power usage of the system as low as possible. For applications which have real time requirements, deterministic response and low power are two of the most important requirements. The thesis is aimed on building an SOC which gives a guaranteed response to any external interrupt that comes. An interrupt controller block, namely NVIS schedules these interrupts by the scheduling algorithm it houses. A 3 stage pipelined processor is developed to process interrupts. The processor is made low power by applying different low power techniques. A bus makes sure that frequency mismatch between the external modules and core doesn’t happen. The complete analysis is done using RTL Compiler tool with NanGate Open cell 45nm library as the default library."
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    Column decoder for memory redundant cell array
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Nahar, Pinky; Nagchoudhuri, Dipankar
    As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy circuit to enhance the reliability for the faulty columns in memory array. The online testing circuit generates the signals for faulty columns, which enables the redundant circuit to replace faulty with spare column of cells. The redundant decoder and multiplexer provide the path to replace the faulty columns with the spare columns. The novel feature of proposed work is that, input of redundant column decoders depends upon the number of bits for a word output instead of the address signals. The proposed circuit provides the reliability with some loss in speed and overhead in terms of chip area. The operating voltage for the design is 3V. The layout and simulations are performed in CADENCE tool for .1μm technology. The performance parameters of various decoders are performed in LT Spice for .18μm technology.
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    Design of CMOS front end for 900MHz RF receiver
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2004) Harshey, Jitendra Prabhakar; Bhatt, Amit
    Portable wireless personal communication systems such as cellular phones, message pagers, and wireless modems traditionally have been built from a mixture of IC technologies. In fact if we section a commercial cellular phone, we could find many separate ICs together linked in the analog section. Moreover some of these ICs are realized on GaAs substrate, others on bipolar Silicon and only the digital section is integrated on CMOS substrate. One of the main challenges facing complete integration of receiver (transmitter) hardware has been a lack of suitable on-chip RF and IF filtering. This approach increases system complexity, cost, and power consumption. The aim of this thesis consists in the investigating the characteristic of RF building blocks that constitute an integrated RF receiver. This thesis, is the balance between microelectronic and microwave, and investigates the bottlenecks in the fully integration of an RF receiver, and is particularly focused on the design of high quality passive devices and high performance low noise amplifiers. This receiver is part of a single chip transceiver, which operates in the 902-928 MHz ISM band. The receiver combines a balanced low-noise amplifier; down conversion mixers, low pass channel-select filters, and IF amplifiers all in one single CMOS IC. Noise components of MOS at high frequencies were studied in detail. Device properties unique to CMOS are exploited to obtain highly linear RF circuits. In design of low noise amplifier, I concentrated my efforts on minimizing the value of passive devices so that all of them can be fabricated on single chip. For this I undertook several optimizations and tradeoffs. Particularly the noise power trade-off with inductors value was stressed on. LNA had three primary design specifications of input impedance matching, gain and noise. I also experimented on several techniques of input match. The results obtained are suited to the needs fairly well. In the mixer design, my primary goal was to design a doubly balanced mixer for single ended inputs. This was necessitated because the antenna signal received was single ended before the LNA and even in LNA, due to several considerations; I obtained a single ended output. Finally this report contains all my designs and simulation results.