Theses and Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/1

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Subject: search.filters.subject.Radio circuits

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Now showing 1 - 5 of 5
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    Radiation analysis of microstrip active (amplifier) and passive (antenna) structures
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dhoot, Vivek; Gupta, Sanjeev
    Analysis of radiation from a microstrip amplifier and a newly proposed microstrip antenna is presented. Microstrip amplifier is analyzed replacing the MMIC structure by an equivalent S2P model and remaining portion being constructed with the original dimensions. A printed monopole antenna using multifractal technique is proposed. This antenna has multiband characteristics covering various wireless applications including WLAN 2.4 GHz and 5.8 GHz applications
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    Design of the analog front end circuit for X-ray detectors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Roy, Subhash Chandra; Parikh, Chetan D.
    The Thesis presents a novel idea to efficiently read out the value corresponding to incident X-Ray, from X-Ray sensor. A system level solution has been proposed which is unique in itself in terms of approach. A simple design of analog front end circuit for 64 channels, consisting of Charge Sensitive Preamplifier (CSP), Pulse Shaping Amplifier (PSA), Peak Detector, subtractor, Mux and ADC has been proposed. In CSP, Transmission Gate (TG) has been used, in parallel with integrating capacitor, where the NMOS is operating in weak inversion, when TG is supposed to be off. It fulfils the requirements like posing very high ac resistance, providing alternative path for DC leakage current signal, discharging integrating capacitor quickly etc. An amplifier cum level shifter has been used to match the output DC level of CSP with input DC level of PSA. PSA has been implemented as a 4th order Bessel-Butterworth low pass filter, which provides good step response, and hence output is obtained with negligible peaking. High pass filter hasn’t been used to avoid low frequency signal loss. A subtractor has been proposed after the peak detector, which is taking care of offset voltages and low frequency noise. This system till the output of shaper is providing a resolution of 1.7% against the specification of 3%.
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    ItemOpen Access
    Design of multi-standard RF front end receiver using novel low IF topology
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Pandit, Vivek Kumar; Gupta, Sanjeev
    This thesis presents the multi-standard receiver architecture and the corresponding RF front-end design supporting Bluetooth and IEEE 802.11a WLAN standards. To maximize the level of component share in the proposed multi-standard receiver, the corresponding standards is analyzed and applied to the proposed multi-standard receiver architecture. Low-IF architecture is chosen for both Bluetooth and IEEE 802.11a WLAN, respectively. The system specifications and the building block specifications is derived from the corresponding standards and verified by spreadsheet models taking into account of major design issues such as image-rejection, intercept points, noise figure and gain. The simulation results prove the validity of the system analysis and the proposed multi-standard receiver architecture.
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    Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sesha Sai, Aduru Venkata Raghava; Parikh, Chetan D.
    In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor using a low-voltage gyrator topology with a feedback resistance, where feedback resistance is realized by a NMOS operating in triode region whose bias voltage tunes the inductance of the active inductor and hence the frequency of VCO. The simulation results shows that this VCO operates in a 1.19 GHz to 2.49 GHz , while consuming 1.09 mW from a 1.2V power supply. The VCO’s phase noise level is -86.9 dBc/Hz at 1 MHz offset from a 1.55 GHz carrier. The deviation of the phase noise is 11.5 dBc/Hz during this tuning range. All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology.
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    Design of low voltage high performance voltage controlled oscillator
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Ramesh, R; Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar
    In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback to achieve high performance in terms of phase noise and output voltage swing. It uses differential MOS varactors for frequency tuning due to which all low frequency noise such as flicker noise gets rejected. Inductor was designed and it was simulated in IE3D electromagnetic simulator to achieve good Quality factor. This VCO achieves a very low phase noise of -119dBc/Hz@1-MHz offset frequency, power consumption of 3.27mW, and tuning range of 6% .All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology