Theses and Dissertations

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Subject: search.filters.subject.Fault tolerance

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    Column decoder for memory redundant cell array
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Nahar, Pinky; Nagchoudhuri, Dipankar
    As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy circuit to enhance the reliability for the faulty columns in memory array. The online testing circuit generates the signals for faulty columns, which enables the redundant circuit to replace faulty with spare column of cells. The redundant decoder and multiplexer provide the path to replace the faulty columns with the spare columns. The novel feature of proposed work is that, input of redundant column decoders depends upon the number of bits for a word output instead of the address signals. The proposed circuit provides the reliability with some loss in speed and overhead in terms of chip area. The operating voltage for the design is 3V. The layout and simulations are performed in CADENCE tool for .1μm technology. The performance parameters of various decoders are performed in LT Spice for .18μm technology.
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    ItemOpen Access
    Realization of FPGA based digital controller
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Patel, Amit; Dubey, Rahul
    Field Programmable Gate Array (FPGA) can be used to enhance the efficiency and the flexibility of digital controller. FPGA implementation of digital controllers leads to real time realizations with small size and high speed. Also it offers advantages such as complex functionality, fast computation, and low power consumption for high volume production. This thesis presents realization of FPGA based speed control of brushless dc (BLDC) motor - a real time application. The construction and the operation of the BLDC motor are described. The different control strategies for speed controller and digital pulse width modulation (PWM) control technique are implemented and tested on BLDC motor. Also their performance is evaluated. Proportional Integral (PI) controller and Fuzzy Logic Controller (FLC) are implemented in FPGA as a digital controller. The PI controller is governed by the values of proportional gain and integral gain, while FLC behaves in much similar way as human controls the system. Logics of both controllers: PI controller and fuzzy logic controller are written in High Description Language (HDL). The performance of the PI controller is better than the fuzzy logic controller in case of the complete known plant.