Theses and Dissertations

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    Low power improved full scan BIST
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Parashar, Umesh; Nagchoudhuri, Dipankar
    Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that influence the heat dissipation during test. This thesis presents a scan-based BIST scheme that reduces switching activity (SA) in the circuit under test (CUT) and test application time without compromising in fault coverage (FC). The proposed BIST scheme is based on combined BIST approach (combining both test-per-scan and test-per-clock test methodologies), two different functional lengths during scan, and a low transition random test pattern generator (LT-RTPG) as TPG. It takes optimal advantage of three techniques and reaches desired FC faster with a significant reduction in switching activity. Experiments conducted on different ISCAS’89 benchmark circuits report up to 24% reduction in SA and up to 80% reduction in the test length. The register transfer level (RTL) implementation of the proposed BIST is done on a 4-bit sequential multiplier circuit (for 90nm technology; Spartan-3 FPGA) to validate effectiveness of the proposed BIST under constraints of supply voltage, glitches, and technology parameters (for 90nm). Experimental results show that proposed BIST achieves 13.75% reduction in the average power dissipation compared to LFSR based BIST.
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    Built-in self-test for a flash analog to digital converter
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Bhalerao, Mangesh; Parikh, Chetan D.
    The intricacies of modern System on Chips (SoCs), comprising of analog, digital and even Redio-Frequency (RF) blocks on a single chip, are surpassing all previous conceivable limits. A more perplexing problem now is not the design but the testing of these SoCs, as the test costs are exceeding all other costs in manufacturing. Digital testing has burgeoned in last forty years into an almost complete science, but analog and mixed-signal and RF testing are still in a precocious state. The dearth of widely accepted standard models, methodologies and Electronic Design Automation (EDA) tools is worsening this situation. This research work tries to suggest and implement an amelioration in Oscillation based Built-In Self-Test, for an analog and mixed signal block i.e., a high speed Analog to Digital Converter (ADC), in deep sub-micron CMOS technology. ADCs are virtually in all modern SoCs and hence are one of the most important modules in analog and mixed-signal designs. A novel Oscillation based Built-In Self-Test is used for testing of a 3-bit 1 GHz CMOS Flash ADC, designed in 0.18 _m CMOS technology. The simulation results prove that this technique shows an excellent coverage of catastrophic as well as a good coverage of parametric faults, with minimal area overhead and lesser test time. The analog and the digital sub-systems of an ADC do not need di_erent test structure, which is its biggest advantage.
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    Statistical delay modeling and analysis for system on chip
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Patel, Jay; Nagchoudhuri, Dipankar
    It is seen that designing using conventional methodologies in Deep Sub Micron geometries, at times, ends up in very pessimistic design and less yield. This is because, today’s tools don’t consider statistical variation of parameters in the fabrication process. IC manufacturer can give probability distribution of such parameters. Using those distributions the tool to be designed will give the probability distribution for delays and slacks. A probabilistic estimation can be made about design functioning in deep sub micron geometries. The delays will have probability distributions based on the parameter variations. These distributions can be found using the way of SPICE simulations. But when circuit complexity increases, these simulations will take a lot of time and it is not the suitable way for large designs. A quick and efficient model has been developed based on MOSFET characteristics. Moreover, a statistical delay model for propagation delay of a gate has also been worked out. Also new methodology and implementation scheme is proposed.
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    Low power BIST architecture for fast multiplier embedded core
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Vij, Aditya; Nagchoudhuri, Dipankar
    A typical core is deeply embedded in the chip of a system so that direct access to its input/output is not possible. Built in self test (BIST) structures are excellent solutions for testing embedded cores. In this work, an 8 ×8 modified Booth multiplier has been implemented with low power test pattern generators (TPG). Complete design was implemented using 0.25-micron technology. The BIST TPG architectures compared were: 8-bit binary counter, 8-bit gray counter and combination of gray and binary counter. Different TPGs have been compared in terms of average power dissipation, fault coverage. Reduction in power dissipation has been achieved by properly assigning the TPG outputs to the multiplier inputs, significantly reducing the test set length and suitable TPG built of a 4-bit binary and 4-bit gray counter. Experimental results show that combination of gray and binary counter can achieve power reduction from 21 %to 45% without affecting the quality of test. BIST architecture for modified Booth multiplier is proposed. Proposed architecture covers stuck at faults, stuck open faults and non-feedback bridging faults. It also provides fault coverage greater than 98 % for stuck-at faults, stuck-open faults and non-feedback faults.
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    ItemOpen Access
    Efficient scan-based BIST scheme for low heat dissipation and reduced test application time
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Shah, Malav; Nagchoudhuri, Dipankar
    Switching activity during test application can be significantly higher than that during normal circuit operation in many circuits. This is due to the fact that the correlation between consecutive test vectors is significantly lower than that between consecutive vectors applied to a circuit during its normal operation. Circuits are increasingly tested at higher clock rates, if possible, at the circuit’s normal clock rates (called at-speed testing). Consequently, the heat dissipation during test application is on the rise and is fast becoming a problem that requires close attention to avoid damaging CUTs. The use of scan DFT can further decrease the correlation between successive vectors applied to the next state inputs. This may lead to hazardous effects such as excessive heat dissipation, increased electro-migration rate and higher ground bounce noise that seriously affects the reliability of the circuit leading to unnecessary loss of yield. This work presents a simple yet efficient low hardware overhead testing scheme for scan-based built-in self-test (BIST) architecture that reduces switching activity in CUTs and test application time without compromising in the fault coverage. Firstly demonstrated is the existing Low Transition Random TPG (LT-RTPG) based test-per-scan scheme targeted for low heat dissipation during test by reducing the number of transitions at the cost of reduced fault coverage. A combined approach using both test-per-scan and test-per-clock application schemes is presented. This improves the fault coverage but at the cost of losing away, to a great extent, the advantage of lesser transitions that was gained using the low transition TPG. Given later is the proposed BIST capability built on top of a partial scan circuit adding above LT-RTPG as the TPG and MISR for signature analysis. This takes optimum advantage of the combined approach. Results show that the proposed BIST scheme gives satisfactory fault coverage (almost comparable to conventional LFSR) that too, with a large reduction in test lengths and transitions.
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    Design of frequency synthesizable delay locked loop
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2004) Shah, Hardik K.; Bhatt, Amit
    As the speed performance of VLSI systems increases rapidly, more emphasis is placed on suppressing skew and jitter in the clocks. Phase-locked loops (PLLs) and delay-locked loops (DLLs) have been typically employed in microprocessors, memory interfaces, and communication IC's for the generation of on-chip clocks. But phase error of PLLs is accumulated and persists for a long time in a noisy environment, that of DLL's is not accumulated, and thus, the Clock generated from DLLs has lower jitter. Therefore, DLLs offer a good alternative to PLL's in cases where the reference clock comes from a low¬ jitter source, although their usage is excluded in applications where frequency tracking is required, such as frequency synthesis and clock recovery from an input signal. Also, the DLLs adjust only phase, not frequency, so the operating frequency range is severely limited. Much work is done to improve the operating range of DLLs, but very less work is done to make DLLs frequency synthesizable. Here, frequency synthesizable DLL is implemented in simplest manner so that it can be useful with least complexity.