Built-in self-test for a flash analog to digital converter

Abstract

The intricacies of modern System on Chips (SoCs), comprising of analog, digital and even Redio-Frequency (RF) blocks on a single chip, are surpassing all previous conceivable limits. A more perplexing problem now is not the design but the testing of these SoCs, as the test costs are exceeding all other costs in manufacturing. Digital testing has burgeoned in last forty years into an almost complete science, but analog and mixed-signal and RF testing are still in a precocious state. The dearth of widely accepted standard models, methodologies and Electronic Design Automation (EDA) tools is worsening this situation. This research work tries to suggest and implement an amelioration in Oscillation based Built-In Self-Test, for an analog and mixed signal block i.e., a high speed Analog to Digital Converter (ADC), in deep sub-micron CMOS technology. ADCs are virtually in all modern SoCs and hence are one of the most important modules in analog and mixed-signal designs. A novel Oscillation based Built-In Self-Test is used for testing of a 3-bit 1 GHz CMOS Flash ADC, designed in 0.18 _m CMOS technology. The simulation results prove that this technique shows an excellent coverage of catastrophic as well as a good coverage of parametric faults, with minimal area overhead and lesser test time. The analog and the digital sub-systems of an ADC do not need di_erent test structure, which is its biggest advantage.