Theses and Dissertations

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    Implementation of ALU using RTL to GDSII flow and on NEXYS 4 DDR FPGA board
    (2021) Kachhadiya, Radhika J.; Parekh, Rutu; Agrawal, Yash
    An ALU is the major part of the CPU which performs various arithmetic and logical operations. It is one of the most frequently used modules in the processor. This paper presents the implementation of 8-bit ALU using RTL to GDSII stream. The tools used for implementation are Cadence tools, Genus and Innovus. The technology node used for implementation is the 45nm technology node and 180nm technology node. The major focus of this thesis is the design optimization in terms of area, delay and power as the industry demands the chips with high speed and low power. Further, the results of both 45nm and 180nm has been compared. The improvement by using 45nm technology in area is 89.59%, in delay is 43.23% and in power is 4.56%. In addition to that, the implementation of 4-bit ALU is done on the FPGA board. The board used is the NEXYS 4 DDR FPGA board.
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    Area efficient and high performance approximate multiplier design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2019) Lad, Pinal Bharatbhai; Agrawal, Yash
    FPGA can provide an efficient way of approximation due to their reprogrammable structure in contrast to ASIC based approximations. The work presents an optimized approximation methodology for multiplier design which utilizes FPGA architecture based designing concept for introducing approximations. This FPGA based approximation approach provides efficient area utilization and higher performance with high accuracy compared to ASIC based approximate multiplier designs. Approximate multipliers are designed on Xilinx Vivado tool, verified on xsim (Xilinx Simulator) and implemented on Artix 7 AC701 FPGA board. For board level implementation of proposed design, virtual input and output core is used to control and monitor inputs and product output interactively for an approximate multiplier 8x8 design running on Artix 7 AC701 FPGA board to overcome limitation of available on-board hardware resources.
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    FPGA based platform for spiking neural network
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Chavada, Sujit; Zaveri, Mazad S
    Neuromorphic engineers are studying the nervous system and trying to emulate its function and organization in their computational and robotics systems. They are hoping to match the human brain in vision, hearing, pattern recognition and learning tasks. Our goal is to create Field Programmeble Gate Array (FPGA) platforms of large-scale spiking neural networks to allow the testing of certain hypotheses related to neuroscience theories. Virtualization is also very important concept for spiking neural network. In this work, we also analyze effect of virtualization on performance and performance/price of spiking neural network. We implement general purpose spiking neural network platform using Spartan 3E FPGA and observe performance and performance/price tradeoffs.
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    FPGA implementation of environment/noise classification using neural networks
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Ambasana, Nikita B.; Zaveri, Mazad S
    The purpose of this thesis is to give an insight into the implementation of a system of neural networks, for the tasks of Noise/Environment Modeling, Feature Extraction and Classification of Noise/Environment, on a Field Programmable Gate Array (FPGA). A methodology for creating baseline architecture for a new system of neural networks has been followed, to give worst case estimates. After necessary analysis an estimate of hardware utilization, within a specific FPGA (XC3S250E Spartan 3E Device) and the Time for Computation, for each of the machines used, is given. It also summarizes the Performance-Price Ratio in terms of Time of Computation and Hardware for Logic simplementation, for different degrees of parallelism in the system.
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    Forward error correction for software defined radio based on FPGA
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Agrawal, Amit H.; Dubey, Rahul
    In digital communication, the signal to noise ratio (SNR) of the channel is one of the major limitations on the operating performance. Solution in terms of coded data and errorcorrecting code has been introduced to improve the performance. Forward error correction technique with Convolution encoding and Viterbi decoding has been introduced here for this purpose. A Convolution encoder and Viterbi decoder of code rate 1/2, constraint length (K) of 7, 8 & 9 has been designed using Verilog HDL and incorporated with our application Software defined radio using black box in MATLAB Simulink. It is important to improve the performance and reduce the power and area of the decoder. In this project, Viterbi decoder adopted the Process Element (PE) technique which made it easy to adjust the throughput of the decoder by increasing or decreasing the number of PE. By the method of Same Address Write Back (SAWB), the number of registers reduced to half in contrast with the method of ping-pong.