Theses and Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/1

Browse

Has files: YesSubject: search.filters.subject.Energy consumption

Search Results

Now showing 1 - 4 of 4
  • Thumbnail Image
    ItemOpen Access
    Design and Simulation of Single Electron Transistor Based High-Performance Computing System at Room Temperature
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2021) Patel, Rashmit; Parekh, Rutu; Agrawal, Yash
    "The VLSI technology has seamlessly grown over the years, that yields high-performance, low-power and high-density devices. Over the several decades, the performance of existing complementary metal-oxide semiconductor (CMOS) technology has been constantly improved by scaling of the transistors size. The scaling and heterogeneous 3D integration aids in achieving high density logic. However, the performance of nanometer scale CMOS based designs is limited due to the short-channel effect, leakage current and process variations. There is a trade-off between speed and power consumption that significantly affects the performance of complex designs like computing devices. The nanoelectronics devices having the capabilities of heterogeneous 3D integration and functional integration with existing technologies serves potential solutions to future silicon technology challenges. These devices can overcome the aforesaid problems and escalates the capabilities of electronics devices in terms of speed, power, density, size and volume. The single electron transistor (SET) is a promising and elegant nano-device which possesses several convincing features such as low energy consumption, efficient operational at room temperature, high switching speed, sustainable with scaling and reduced operating potentials to compete or outperform conventional CMOS technology. The SET can be used as basic element in either individual circuit or hybrid circuit with existing CMOS technology. The survey of individual SET based designs shows that these are at smaller block level with improper SET parameters, operating temperature, interconnect parasitics, etc. The bottleneck with SET based designs having thousands of gates, is unavailability of either dedicated electronic design automation (EDA) tool or standard component library or synthesizer. This research gap is accomplished by proposed SET based computing system with consideration of realistic SET parameters and interconnects parasitics at room temperature operation.The SET based computing system design is accomplished by utilizing industry standard Cadence Virtuoso analog design environment (ADE). It is carried out with gate level abstraction of SET Verilog-A behaviour model. The generated SET symbol is used to design basic combinational and sequential elements. The higher order circuit blocks of computing system are realized with these elements. Finally, a computing system is realized with integration of these foundation circuit blocks. The computing system is analyzed for a set of multiple instructions i.e. program level with the help of a developed tool. The proposed design is carried out at transistor level abstraction. The formulated analytical model is performed for SET and it matches very closely with simulation model results. The each of the design block is verified for timing analysis. Also, the parametric analysis is compared with other research works. The proposed SET based computing system is considerably better with higher operating frequency (around 5 times), lower power dissipation (around 1.6 times) and higher execution of instruction per second (around 5 times) than its counterpart 16 nm CMOS technology. To check the robustness of the SET based computing system, variability analysis has been performed. It is observed that SET based computing system is less immune to supply voltage variations. This can be compensated by applying suitable voltage regulation techniques. On the other hand for temperature and process variations, it is envisaged that the SET based computing system is very robust. Hence, it is inferred that variability issues are very lesser in SET based systems and can be good alternative to replace conventional systems. Through the SET based design approach, integrated circuit can pack greater functionality with higher operating speed, smaller footprint, lower power consumption and lesser thermal budget."
  • Thumbnail Image
    ItemOpen Access
    Traffic driven topology control for network lifetime maximization
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Agrawal, Rupesh; Srivastava, Sanjay; Muthu, Rahul; Muthu, Rahul
    Energy consumption is a major concern in ad hoc wireless networks. Network life-time can be maximized by minimizing the network power consumption. Topology control is one of the most important mechanisms used for reducing network power consumption. Topology control can be achieved either by transmit power control or sleep scheduling. In transmit power control the optimization problem is to find the transmission power at which the power consumption is minimized while maintaining desired connectivity. In sleep scheduling, nodes which are redundant are switched on and off using a scheduling algorithm. One of the main problem with sleep scheduling is whenever the traffic pattern changes, path going through awake nodes may become longer while there may exist a shorter path considering some of the sleeping nodes. This will increase per packet transmission energy consumption as well as end to end delay. In this thesis we propose a traffic aware topology control protocol to solve this problem. It finds out subset of sleeping nodes to be awakened on the basis of current traffic scenarios so that total traffic weighted network cost can be minimized at global level hence saving the overall energy of the network and maximizes the network life- time. Simulation results show that,our proposed protocol is able to save a signicant amount of energy while maintaining end to end packet delay.
  • Thumbnail Image
    ItemOpen Access
    Power management of wireless sensor node by dynamic power measurement
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Kapasi, Jay; Ranjan, Prabhat
    Wireless sensor network(WSN) is a collection of spatially distributed autonomous sensor nodes, which cooperatively monitor physical or environmental conditions, such as temperature, sound, vibration, pressure, motion or pollutants. As Wireless sensor node cannot be connected to a large source of power supply, they have to run on portable energy sources such as solar cell and batteries. Thus it is very important to minimize the use of power in each individual node of network as even a single point of power failure may prove to be a great loss of functionality. Even though minimization of power consumption may appear to be a complex problem, due to advances in technology and availability of devices with different low power states, it has become a simplified matter of just determining the power state of each device in system to minimize power consumption. The work presented here shows an implementation of a power aware wireless sensor network. Power is measured dynamically in sensor node as certain events trigger the addition of new loads.
  • Thumbnail Image
    ItemOpen Access
    Lifetime analysis of wireless sensor nodes using queuing models
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Anand, Guneshwar; Srivastava, Sanjay
    Prolonging the lifetime of wireless sensor networks (WSN) is one of the key issues for wireless sensor network applications. For increasing the lifetime of network, each node should conserve its energy. Sensor nodes consume different power in different operating modes. It also consumes significant amount of power while switching from one mode to another mode. So it is important that how frequently a node is changing its mode. To address this question we have used queuing theory based control policy, which finds the optimal parameter for switching between modes. We have analysed two different control policies namely, N-policy and T-policy and their effect on the lifetime of a sensor node. In N-policy, a sensor node switches its mode only when total number of packets are N. We find an optimal value of N that minimizes the energy consumption per unit time. Similarly, in T-policy whenever system becomes empty it goes on vaccation for a fixed duration T. It changes its mode only again after T unit of time and stays in the same mode as long as there is a packet. In this case also we find the optimal value of T that minimizes the energy consumption per unit time. But this improvement in lifetime comes at the cost of longer delay and larger waiting time. We have given the expression for the latency delay. Depending on the application requirement one can tune the parameters to get the best result between the energy saving and latency delay.