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Permanent URI for this collectionhttps://ir.daiict.ac.in/handle/123456789/37
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Publication Metadata only Capacity of a quantum memory channel correlated by matrix product states(Springer, 2018-04-01) Mulherkar, Jaideep; V, Sunitha; DA-IICT, GandhinagarWe study the capacity of a quantum channel where channel acts like controlled phase gate with the control being provided by a one-dimensional quantum spin chain environment. Due to the correlations in the spin chain, we get a quantum channel with memory. We derive formulas for the quantum capacity of this channel when the spin state is a matrix product state. Particularly, we derive exact formulas for the capacity of the quantum memory channel when the environment state is the ground state of the AKLT model and the Majumdar�Ghosh model. We find that the behavior of the capacity for the range of the parameters is analytic.Publication Metadata only A 46 nW power management unit with battery extender for solar energy harvesters using 0.18 ?m CMOS(American Scientific Publishers, 01-06-2018) Patel, Purvi; Mishra, Biswajit; nagchoudhuri, Dipankar; DA-IICT, Gandhinagar; Patel, Purvi (201521008)This work presents the design of an ultra low power (ULP) management unit to be used in conjunction with tiny solar energy harvesters (EH) providing very low power for energy autonomy in wireless sensor applications. The power management unit (PMU) is designed using 0.18 ?m CMOS in subthreshold region of MOSFET for reduced power consumption and increased efficiency. A battery extender module is also implemented to obtain continuous power in the absence of energy harvesting source. The PMU achieves a maximum of 72.3% efficiency and has a response time of 5.8088 s and 13.03 ms at the input voltages of 0.98 and 1.33 V, regulating the output voltage at 0.95 V and 0.968 V, respectively. The proposed PMU consumes 46 nW and 68 nW along with the battery extender, at input voltages of 0.98 V and 1.33 V, respectively, thereby making it suitable for ultra low voltage and low power applications.Publication Metadata only Customized IoT Enabled Wireless Sensing and Monitoring Platform for Smart Buildings(Elsevier, 01-04-2017) Shah, Jalpa; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; DA-IICT, Gandhinagar; Shah, Jalpa (201121001)In this paper we present a customized Internet of Things (IoT) enabled Wireless Sensing and Monitoring Platform to monitor the temperature, relative humidity and light in the context of building automation. In developed system, data is sent from the transmitter node to the receiver node through a customized hopping method. The data received at the receiver node is monitored and recorded in an excel sheet in a personal computer (PC) through a Graphical User Interface (GUI), made in LabVIEW. An Android application has also been developed through which data is transferred from LabVIEW to a smartphone through which data is remotely monitored.Publication Metadata only Light-weight configurable architecture for QRS detection(IET, 01-03-2019) Jain, Nupur; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; DA-IICT, Gandhinagar; Jain, Nupur (201221008)In this study, the authors present a configurable architecture having gate count of ?3.2??? and on the fly reconfigurability for low-power biomedical applications such as QRS detection, ExG processing etc. The proposed architecture is a light-weight co-processor that supports on-node digital signal and image processing functions potentially eliminating the power consumed by radios in wireless sensor node and body sensor network. The architecture consists of a 3?�?3 array of register units along with adaptive memory with configurable data path. The architecture can be configured on-the-fly for seven functions with the current memory structure. However, more number of functions can be targeted with increased memory. They demonstrate the realisation of Pan�Tompkins algorithm commonly used for QRS detection on the proposed architecture using the reconfigurability. This work offers ?4� reduced area and 2.3� increase in performance with respect to the existing contemporary literature.Publication Metadata only Ultra-low power digital front-end for single lead ECG acquisition integrated with a time-to-digital converter(IET, 16-07-2019) Mishra, Biswajit; Thakkar, Sanket; Jain, Nupur; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; DA-IICT, Gandhinagar; Thakkar, Sanket (201611046); Jain, Nupur (201221008)A low power single lead electrocardiogram front-end acquisition system in 0.18 ?m CMOS operating at 0.5 V is presented here. The analogue blocks in low noise amplifier (LNA), filters and passive elements that perform amplification and DC offset cancellation are replaced by a moving average voltage to time converter (MA-VTC) to get amplification and anti-aliasing in the time domain. A digital feedback algorithm is used to cancel out the DC offset. The front-end structure is designed in the sub-threshold region of MOS to reduce the power consumption in the circuit. The proposed architecture consumes 50 nW of power with a gain of 670 ?s/V. The output of the front-end is fed to an all digital time-to-digital converter (TDC) that operates in the near threshold region with a resolution of 586.4 ps and 32.5 ?W power consumption.Publication Metadata only CMOS Power Management Unit Along with Load Regulation Using Switched Capacitor Converters(American Scientific Publishers, 01-06-2019) Patel, Purvi; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; DA-IICT, Gandhinagar; Patel, Purvi (201521008)In this paper, a power management unit (PMU) with battery backup and output load regulation using switched capacitor converters using 0.18 m Complimentary Metal Oxide Semiconductor technology is presented. Low power consumption is obtained by employing subthreshold design methods. The main building blocks of the PMU are a voltage regulator, a voltage monitor, a battery backup and switched capacitor (SC) converters. The voltage regulator has an output voltage VOUT at 0.95 V and 0.968 V at input voltages of 0.98 V and 1.33 V, respectively. Perpetual operation at the load side is confirmed by implementing a battery backup module, which provides the battery voltage to the load circuit when the output voltage of the energy harvesting (EH) source is insufficient. The presented PMU consumes 46 nW at 0.98 V and 3.919 W with SC converters at 1.33 V. Different voltages can be tapped from the PMU from the 3:2, 2:1, 3:1, 4:1 and 5:1 down converters that provide output voltages of 0.67 V, 0.5 V, 0.33 V, 0.25 V and 0.2 V to the load, respectively. The maximum current that can be delivered by the PMU is 1 mA at an input voltage of 1.33 V and is adequate for many low power applications.Publication Metadata only A novel signal processing coprocessor for n-Dimensional geometric algebra applications(SCIRP, 01-11-2014) Mishra, Biswajit; Kochery, Mittu; Wilson, Peter; Wilcock, Reuben; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; DA-IICT, GandhinagarThis paper provides an implementation of a novel signal processing co-processor using a Geome-tric Algebra technique tailored for fast and complex geometric calculations in multiple dimensions. This is the first hardware implementation of Geometric Algebra to specifically address the issue of scalability to multiple (1 -8) dimensions. This paper presents a detailed description of the imple-mentation, with a particular focus on the techniques of optimization used to improve performance. Results are presented which demonstrate at least 3x performance improvements compared to previously published work.Publication Metadata only A Low Power Wearable Device for Real-Time Electrocardiogram Monitoring and Cardiovascular Arrhythmia Detection for Resource Constrained Regions(American Scientific Publishers, 01-06-2019) Arora, Neha; Mishra, Biswajit; Vora, Yash; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; DA-IICT, Gandhinagar; Arora, Neha (201721007); Vora, Yash (201711043)Electrocardiography is a non-invasive technique for obtaining the electrical activity of heart by placing electrodes on various thoracic points of human body. The obtained electrical signals are then used to detect various cardiovascular abnormalities i.e., arrhythmias, Myocardial Infarction (MI) conditions, hypercalcemia and hypocalcemia etc. by comparing critical features of normal ECG signals with the abnormal one. In this work, we propose a low power wearable device with two transmission channels that runs an intuitive algorithm and processes the data from a single lead ECG front end (extended upto 3 Leads) and reports various arrhythmic conditions based on R�R interval. Pan Tompkins Algorithm is used as the basic R peak detection scheme and extending detections of P wave, T wave, Q, S and J points of the signal. To verify the proposed algorithm, the MIT/BIH arrhythmia database is used as a source of the ECG signals and the reference for R peak annotations. The R peak detection algorithm provides metric of False Detection Rate to be 1.289%, Sensitivity to be 99.492% and Positive Predictivity to be 99.293%. The energy requirement for ISM band enabled wearable device is 1.4165 J and bluetooth enabled wearable device is 2.7548 J respectively and the device can operate for 12.3 days on nRF and 4.2 days on bluetooth on a coin cell and can prove to be effective for remote monitoring applications. Results for arrhythmia, I degree atrioventricular block (AV block) and atrial fibrillation (AF) have been obtained. The probable cases of bundle branch block (BBB) are also categorized by the algorithm. It is concluded that the proposed low power wearable device design can be a useful tool in the resource constraint regions in Asia and Africa where health care is a major concern and remote monitoring can prove to be a useful alternative.Publication Metadata only A geometric algebra co-processor for color edge detection(MDPI, 01-01-2015) Mishra, Biswajit; Wilson, Peter; Wilcock, Reuben; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; Mishra, Biswajit; DA-IICT, GandhinagarThere is a lot of discussion on the effect of computers and Internet on students' academic performance but few in the context of the Indian scenario. Hence a study was conducted, of two groups of private engineering university students (345 respondents from each university). They were surveyed by administering online questionnaires, following a smaller pilot study to fine-tune the survey instrument. The main purpose of the research was to understand student behaviors related to time spent on computers and their relationship to academic performance. The data indicates that there is a correlation between academic performance and excessive use of Internet. The impact of faculty/student interaction and its relationship to academic performance needs further exploration.Publication Metadata only Affine interpolation in a lie group framework(ACM, 12-07-2019) Bansal, Sumukh; Tatu, Aditya; Tatu, Aditya; Tatu, Aditya; Tatu, Aditya; Tatu, Aditya; Tatu, Aditya; DA-IICT, Gandhinagar; Bansal, Sumukh (201421002)Affine transformations are of vital importance in many tasks pertaining to motion design and animation. Interpolation of affine transformations is non-trivial. Typically, the given affine transformation is decomposed into simpler components which are easier to interpolate. This may lead to unintuitive results, while in some cases, such solutions may not work. In this work, we propose an interpolation framework which is based on a Lie group representation of the affine transformation. The Lie group representation decomposes the given transformation into simpler and meaningful components, on which computational tools like the exponential and logarithm maps are available in closed form. Interpolation exists for all affine transformations while preserving a few characteristics of the original transformation. A detailed analysis and several experiments of the proposed framework are included.