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Reliability Assessment using Electrical and Mechanical Characterization of Stretchable Interconnects on Ultrathin Elastomer for Emerging Flexible Electronics System
(IEEE, 10-07-2025) Bhatti, Gulafsha; Sharma, Rohit; Kumar, Mekala Girish; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, Gandhinagar
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Signal Integrity Analysis of Biodegradable Stretchable Interconnect for Wearable Application
(IEEE, 01-07-2025) Bhatti, Gulafsha; Maru, Devkaran; Patle, Kamlesh; Shah, Kinnaree; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, Gandhinagar
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Explicit Analytical Model of Stretchable Interconnects for Flexible Electronics System
(IEEE, 24-07-2025) Bhatti, Gulafsha; Kumar, Mekala Girish; Sharma, Rohit; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, Gandhinagar
A printed circuit board (PCB) is one of the strong backbones to execute electronic system designs. Due to fast and reliable communication requirements between integrated circuit and other peripheral components over the PCB, there is a quest for the development of board-level designs and layouts. The advancement in technology has led to inventions from conventional rigid to flexible PCBs or flexible electronics (FE). The conformability of FE circuitry majorly depends upon the stretchable interconnects. An interconnect is the medium through which a signal is transmitted. The characteristic of stretchable interconnects is determined through their electrical and mechanical properties. The analytical model and parasitic extraction of the interconnect for rigid PCB structures have been widely explored earlier. However, the analytical formulation of the stretchable interconnect still remains a challenge and meagerly explored till date. Consequently, in this work, an explicit analytical model for the parasitic extraction of stretchable interconnects, viz., resistance (R), inductance (L), and capacitance (C), under stretching and bending effects has been novelly proposed. Five different interconnect materials have been considered for the analysis. The analytical model results have been validated with the ANSYS EDA tool. It is investigated that the proposed analytical model results are in very close agreement with the ANSYS results for all the considered cases.
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Impact of Electrode Patterns Variation on the Response Characteristic of Leaf Wetness Sensors
(IEEE, 05-08-2024) Patle, Kamlesh S; Sharma, Neha; Khaparde, Priyanka; Varshney, Harsh; Bhatti, Gulafsha; Agrawal, Yash; Palaparthy, Vinay; DA-IICT, Gandhinagar; Patle, Kamlesh S(202121017); Sharma, Neha (202211051); Varshney, Harsh (202211001); Bhatti, Gulafsha (202021005)
Prediction of plant diseases is essential to reduce crop loss. Early disease prediction models have been investigated for this purpose, where data on leaf wetness duration (LWD) is one of the key components. Leaf wetness sensors (LWSs) are used to better understand how foliar wetness affects plant disease cycles and epidemic development. LWS can be fabricated on printed circuit boards (PCBs), where interdigitated electrode patterns are widely used. However, it is important to understand the efficacy of these patterns for in-situ measurements. For this purpose, in this work, we have fabricated three different patterns viz. circular, oval, and rectangular on the PCB and tested their efficacy during lab and field measurements. Lab measurements indicate that the circular patterned LWS offers a sensitivity of about 1600% over the dry-to-wet range, which is about 2 and 1.5 times more than oval and rectangular patterns, respectively. Besides this, circular patterned LWS offers the hysteresis of about 2%, whereas the oval and rectangular patterned LWS show about 3% and 7%, respectively. Field measurement results specify that circular patterned LWS and commercial LWS Phytos 31 indicate the same number of LWD events. However, oval and rectangular patterned LWS shows extra false events.
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Neural Network-based Fast and Intelligent Signal Integrity Assessment Model for Emerging MWCNT Bundle On-Chip Interconnects in Integrated Circuit
(Taylor & Francis, 26-02-2023) Bhatti, Gulafsha; Pathade, Takshashila; Agrawal, Yash; Palaparthy, Vinay; Gohel, Bakul; Parekh, Rutu; Kumar, Mekala Girish; DA-IICT, Gandhinagar; Gulafsha Bhatti (202021005); Takshashila Pathade (201621013)
At nanometer technology nodes, the efficient signal integrity and performance assessment of vast on-chip interconnects are crucial and challenging. For a long time, copper (Cu) has been used as an interconnect material in integrated circuits (ICs). However, as heading towards lower technology nodes, Cu is becoming inadequate to satisfy the requirements for high-speed applications due to its physical limitations. To mitigate this issue, a multiwall carbon nanotube bundle (MWCNTB) is proven to be a better replacement for Cu. Hence, the current work innovatively focuses on modeling, analysis, and performance evaluation of MWCNTB interconnects at 32?nm technology nodes using various machine learning (ML) and neural network (NN) based techniques for signal integrity assessment and fast computation of on-chip interconnect design. Based on the results obtained by comparing the different performance parameters, it is envisaged that NN-based ADAM technique leads to the best-suited model. The developed model is fruitful in evaluating the output performance of the system, such as power-delay-product (PDP), performing parametric analysis, and predicting optimum input design parameters of the driver-interconnect-load (DIL) system. This work utilizes HSPICE and Python electronic design automation tools for its implementation.

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