M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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    Built-in self-test for a flash analog to digital converter
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Bhalerao, Mangesh; Parikh, Chetan D.
    The intricacies of modern System on Chips (SoCs), comprising of analog, digital and even Redio-Frequency (RF) blocks on a single chip, are surpassing all previous conceivable limits. A more perplexing problem now is not the design but the testing of these SoCs, as the test costs are exceeding all other costs in manufacturing. Digital testing has burgeoned in last forty years into an almost complete science, but analog and mixed-signal and RF testing are still in a precocious state. The dearth of widely accepted standard models, methodologies and Electronic Design Automation (EDA) tools is worsening this situation. This research work tries to suggest and implement an amelioration in Oscillation based Built-In Self-Test, for an analog and mixed signal block i.e., a high speed Analog to Digital Converter (ADC), in deep sub-micron CMOS technology. ADCs are virtually in all modern SoCs and hence are one of the most important modules in analog and mixed-signal designs. A novel Oscillation based Built-In Self-Test is used for testing of a 3-bit 1 GHz CMOS Flash ADC, designed in 0.18 _m CMOS technology. The simulation results prove that this technique shows an excellent coverage of catastrophic as well as a good coverage of parametric faults, with minimal area overhead and lesser test time. The analog and the digital sub-systems of an ADC do not need di_erent test structure, which is its biggest advantage.
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    Statistical delay modeling and analysis for system on chip
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Patel, Jay; Nagchoudhuri, Dipankar
    It is seen that designing using conventional methodologies in Deep Sub Micron geometries, at times, ends up in very pessimistic design and less yield. This is because, today’s tools don’t consider statistical variation of parameters in the fabrication process. IC manufacturer can give probability distribution of such parameters. Using those distributions the tool to be designed will give the probability distribution for delays and slacks. A probabilistic estimation can be made about design functioning in deep sub micron geometries. The delays will have probability distributions based on the parameter variations. These distributions can be found using the way of SPICE simulations. But when circuit complexity increases, these simulations will take a lot of time and it is not the suitable way for large designs. A quick and efficient model has been developed based on MOSFET characteristics. Moreover, a statistical delay model for propagation delay of a gate has also been worked out. Also new methodology and implementation scheme is proposed.
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    Low power BIST architecture for fast multiplier embedded core
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Vij, Aditya; Nagchoudhuri, Dipankar
    A typical core is deeply embedded in the chip of a system so that direct access to its input/output is not possible. Built in self test (BIST) structures are excellent solutions for testing embedded cores. In this work, an 8 ×8 modified Booth multiplier has been implemented with low power test pattern generators (TPG). Complete design was implemented using 0.25-micron technology. The BIST TPG architectures compared were: 8-bit binary counter, 8-bit gray counter and combination of gray and binary counter. Different TPGs have been compared in terms of average power dissipation, fault coverage. Reduction in power dissipation has been achieved by properly assigning the TPG outputs to the multiplier inputs, significantly reducing the test set length and suitable TPG built of a 4-bit binary and 4-bit gray counter. Experimental results show that combination of gray and binary counter can achieve power reduction from 21 %to 45% without affecting the quality of test. BIST architecture for modified Booth multiplier is proposed. Proposed architecture covers stuck at faults, stuck open faults and non-feedback bridging faults. It also provides fault coverage greater than 98 % for stuck-at faults, stuck-open faults and non-feedback faults.