M Tech Dissertations
Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3
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Item Open Access Design of the high speed, high accuracy and low power current comparators(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Chasta, Neeraj Kumar; Parikh, Chetan D.Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”. A current comparator can be referred as trans-impedance amplifiers which compares applied input currents and generate CMOS compatible output voltage. In this work, study and simulations of various current domain comparator circuits have been done; some of these follow basic analog circuit concepts like current mirroring and Voltage current feedback. This thesis presents a novel idea for analog current comparison with controlled hysteresis. Proposed circuit is based on current mirror and latching techniques. Comparator presented is designed optimally in 0.18μm CMOS process in LTspice environment. Designing issues have also been discussed for no hysteresis (or very less hysteresis) case, where comparator gives higher accuracy and speed at the cost of increased power consumption. In addition to this a simple circuit is proposed which satisfies high speed, high accuracy and low power consumption constraints for the mentioned technology parameters. It utilizes amplification properties of Common gate circuit for generating CMOS compatible output voltage by comparison of applied input signal current and reference currentItem Open Access High speed, low offset voltage cmos comparator(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Sheikh, Parveen; Parikh, Chetan D.The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is generally limited by the speed and precision with which the function of comparison can be performed. Thus, comparator speed and precision play a vital role in high performance ADC’s. CMOS comparators suitable for integration in VLSI technologies have been successfully realized for audio frequency applications, such as analog - to-digital (A/D) converters. The speed and resolution of MOSFET comparators are typically limited by the inherent MOSFET characteristics of low trans-conductance and relatively large device mismatches. However, there are several techniques for dynamic offset cancellation, dynamic biasing, and analog pipelining which significantly improve the speed and resolution achievable in an MOS based comparator. The thesis proposes a novel approach which minimizes the offset of pre-amplifier as well as the latch with increment in the speed of the comparator. The total offset thus referred back to the input is minimized and hence the pre-amplifier gain be relaxed. The CMOS circuit is implemented in 0.18 μm technology and simulated in LT-Spice.Item Open Access High-performance low-voltage current mirror design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Gandhi, Nikunj; Parikh, Chetan D.Design of high precision analog circuits requires accounting for the mismatch between nominally identical transistors. In this work, errors affecting CMOS current mirrors due to mismatch between identical transistors are discussed, and circuit techniques to overcome these errors are studied. The dynamic current mirror (DCM) is one of the solutions to overcome mismatch problems. Dynamic current mirrors contain analog and digital components together so that errors due to process variations, temperature and ageing effect can be cancelled. Various circuit techniques such as op-amp based DCM, reduced transconductance based DCM, and cascode based DCM have been used to improve the performance of current mirrors. This thesis proposes a novel circuit for a low-voltage high-performance dynamic current mirror design. The thesis investigates the performance of analog switches at low voltages, and suggests an improved bootstrap switch; errors due to clock feed through and charge injection in the switch are analysed. A new low charge injection, voltage-boosted analog switch is recommended in the dynamic current mirror design. A bulk-driven dynamic current mirror circuit is proposed, and found to be an effective solution at low voltage. The proposed circuit is designed optimally in a 0.18µm CMOS process, in the Cadence Spectre environment. A current copying accuracy of ±0.14% is achieved under worst case conditions.Item Open Access Test methodology for prediction of analog performance parameters(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Akula, Sandeep; Nagchoudhuri, DipankarAnalog testing, the name itself signifies the detection of faults in analog circuits. The aim of this thesis is to increase the test effectiveness and work in the performance parameter space. There are many test methodologies which can detect the faults in the circuit under test (CUT), out of which the test methodologies which can determine CUT performance parameters resulting in enhanced test effectiveness are, predictive oscillation based test methodologies. To detect the catastrophic and parametric faults these methodologies are used. These test methodologies are preferred over other methodologies because the input test stimulus generation is not needed, which reduces the complexity if multiple inputs are applied to the circuit. These test techniques are implemented with prediction process using neural networks which will in turn increases the performance of the circuit under test. The thesis follows with the implementation of the techniques and understanding the methods to increase the test effectiveness. The design process is performed in CADENCE simulation tool with 180nm technology.Item Open Access 1v rail to tail operational amplifier design for sample and hold circuits(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Kumar, Mahesh; Parikh, Chetan D.At low voltage, the input common mode voltage of Operational amplifier is limited which restricts its use as a buffer. This works deals with designing a rail to rail amplifier. The Thesis presents a 1V rail to rail operational amplifier that has been used as a unity gain buffer in the sample and hold circuit for 1V 10 bit 1MSPS pipeline ADC in 0.18?m technology. The Operational amplifier is designed using dynamic level shifting technique which uses an additional input CM adapter circuit for fixing the input common mode voltage. Novelty in the input CM adapter circuit and a low value of gm fluctuation (�0.245%) has been achieved. The Operational amplifier is implemented in standard CMOS technology. An open loop architecture is chosen for the implementation of sample and hold circuit. The transmission gate switch is used in the sample and hold circuit for reducing the effect of channel charge injection and clock feedthrough. Also, the transmission gate switch offers a low resistance as compared to pMOS or nMOS switches. The sample and hold circuit speed up to 1MSPS has been achieved.Item Open Access Design of low voltage high performance, wide bandwidth current feedback amplifier with complementary input pair(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Dubey, Divya; Parikh, Chetan D.This thesis presents the work done on the design of a low voltage high performance, wide bandwidth current feedback amplifier [CFA] with complementary input pair. The design is carried out in 1.8 V, 0.18 micron CMOS process. The design uses the cascaded voltage follower configuration that improves the bandwidth of the amplifier and to get almost rail-to-rail input swing capability, parallel NMOS and PMOS differential pairs are used with current addition. Thus proposed current feedback amplifier combines the advantages of both the design. It provides wide bandwidth and simultaneously increases the input voltage range. It also provides low power consumption and high transimpedance. Simulation results show that the closed loop bandwidth for unity gain noninverting configuration is 458 MHz and the input voltage range is from –0.8 to 0.35 V, for supply voltages ranging from +0.9 to –0.9 V. The amplifier performance is also evaluated to see the gain bandwidth independence effect. This CFA provides almost gain independent closed loop bandwidth, which depends on the value of feedback resistor.Item Open Access Frequency compensation technique for low voltage three stage operational amplifier(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Kunde, Raju; Parikh, Chetan D.This thesis presents a new frequency compensation technique for low supply voltage three-stage operational amplifier at higher loads. It is based on the miller splitting and pole-zero cancellation using feed-forward path. To reduce the value of compensation capacitance feedback stage is added in series with the compensation capacitance. The amplifier exhibits a dc gain 72db,a gain bandwidth of 35MHz at 63 degree phase margin slew rate 1 v/sμ, a compensation capacitance 4.5pF and load capacitance 300pF while consuming 395Wμat a 1-V supply voltage.Item Open Access Extremely low voltage operational amplifier design with rail-to-rail input common mode range(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Malviya, Yogesh; Nagchoudhuri, DipankarIncreasing trends towards battery operated systems demand circuits to be designed at low voltages. Low voltage operation severely limits the operational amplifier as a voltage buffer as the input common mode range available is very limited. This work deals with designing a very low voltage amplifier that can be used as a unity gain buffer. The architecture is based on using an operational amplifier in conjunction with an adapter circuit. The compliance voltage of the tail current source is maintained constant by comparing with a reference voltage using negative feedback action. The amplifier has been designed in 0.18µm technology at a supply voltage of 0.8 Volts. The amplifier gives a constant performance for varying common mode voltage as is demanded for a rail-to-rail amplifier. Designed amplifier gives a gain of 77.4dB with an input stage transconductance ‘Gm’ variation of just 1.29 % over the entire input common mode range.Item Open Access Design of a low power high slew rate OPAMP and to study its impact on sigma delta modulator's performance(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Verma, Aseem; Parikh, Chetan D.This thesis presents the work done on the design of a low-power, high slew rate opamp and subsequently the design of a fully-differential second order Switched-Capacitor architecture of a Sigma Delta modulator in 1.8 V, 0.18 micron CMOS process. A nonsaturated differential input stage is used as an adaptive bias circuit in a Super Class AB opamp, implemented in fully-differential configuration using high swing cascade mirrors. Comparator and clock generating circuit are also designed for the modulator. Various design aspects such as clock feed through, charge injection and KT/C noise have been taken into consideration while designing the modulator. Inaccurate and Incomplete charge transfer in integrator due to bandwidth and slew rate limitations results in gain error and harmonic distortion respectively in the modulator output. Thereby reducing the Signal to Noise and Distortion Ratio of the modulator. Hence Slew rate must be large enough so that the distortion introduced falls below the noise floor of the modulator. Simulation results show that the amplifier has a very small static power dissipation of 0.54 mW, it can supply a maximum output current of 0.65 mA and static power dissipated by sigma delta modulator is 2.7 mW.Item Open Access Low power high speed amplifier design(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Bensal, Jitendra Babu; Nagchoudhuri, DipankarThe operational amplifier (op-amp) is one of the important component in analog to digital converters. The power consumption of these converters mostly depend on the op-amps used. The accuracy and speed performance of analog to digital converters can also be affected due to the finite DC gain and finite bandwidth of the opamp. So the design of op-amp is very critical for these applications. This thesis describes the design of a telescopic operational amplifier. Of the several architectures, a telescopic operational amplifier provides better frequency response and also consumes least power in comparison with other topologies. The limited swing of the telescopic amplifier has been improved by using the current source load transistors in the linear region. Two gain boosting amplifiers are also used to enhance the gain of the amplifier. This gain boosting amplifiers uses a folded - cascode topology. The overall circuit is designed in 0.18 micron CMOS technology at a supply voltage of 1.8 Volt. The operational amplifier achieves a dc gain of 72 dB, bandwidth of 390 MHZ, slew rate of 132 V/ µs and a differential output swing of ± 0.82 V. The overall circuit consumes a total power of 3.36 mw.