M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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    Design & layout of a low voltage folding & interpolation ADC for high speed applications
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Tiwari, Sandeep Kumar; Sen, Subhajit
    Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) plays a vital role in mixed analog signalling, communication and digital signal processing world. Now a day, the demand for designing of high speed, low power and low voltage ADCs are increasing tremendously in high speed data processing applications. In the folding and interpolation ADCs folding amplifiers have the serious bandwidth limitation problem because of larger parasitic capacitance and resistance at the output node. In this thesis work a low voltage and high speed folding and interpolation ADC is implemented using current steering CMOS folding amplifier followed by transresistance amplifier (TRA) in UMC 180nm CMOS technology. The current steering folding amplifier significantly reduces power as well as number of tail current sources compared to the conventional folding amplifier. Transresistance amplifier, which is connected at the output of folding amplifier, avoids the analog bandwidth limitation problem. MSB and LSB bits are generated simultaneously at the output therefore sample and hold circuit is not required in this architecture. This proposed circuit works at 1.8V power supply and 85 MSamples/S and consumes 70mW power. Simulation and Layout of Folding and Interpolation ADC were done using UMC CMOS 180nm technology in the Cadence Analog Design Environment
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    High speed sample and hold circuit design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dwivedi, Varun Kumar; Parikh, Chetan D.
    Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its front-end component. In this thesis, the high speed sample and hold circuit has been designed, requiring low power as a front end block of pipeline analog to digital converter. In this work, architectures of sample and hold circuit are studied and issues which limit the performance of sample and hold circuits are discussed. A fully differential S/H circuit using bottom plate sampling is proposed. The circuit has been designed in order to meet the specification. Amplifiers are studied and folded-cascode amplifier is chosen as an optimum architecture for switch capacitor based sample and hold circuit. The proposed circuit is designed optimally in a 180 nm CMOS process, in the Cadence Spectre environment. The speed and power achieved are 125 MSPS, 6.8mW respectively.
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    Test methodology for prediction of analog performance parameters
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Akula, Sandeep; Nagchoudhuri, Dipankar
    Analog testing, the name itself signifies the detection of faults in analog circuits. The aim of this thesis is to increase the test effectiveness and work in the performance parameter space. There are many test methodologies which can detect the faults in the circuit under test (CUT), out of which the test methodologies which can determine CUT performance parameters resulting in enhanced test effectiveness are, predictive oscillation based test methodologies. To detect the catastrophic and parametric faults these methodologies are used. These test methodologies are preferred over other methodologies because the input test stimulus generation is not needed, which reduces the complexity if multiple inputs are applied to the circuit. These test techniques are implemented with prediction process using neural networks which will in turn increases the performance of the circuit under test. The thesis follows with the implementation of the techniques and understanding the methods to increase the test effectiveness. The design process is performed in CADENCE simulation tool with 180nm technology.
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    Built-in self test architecture for mixed signal systems
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Jain, Mahavir Rajmal; Mandal, Sushanta; Nagchoudhuri, Dipankar
    Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and used for digital circuitry due to well defied fault models and advanced designs tools and techniques available. But with more analog circuitry being built on same platform with digital circuitry, the necessity for BIST architecture of mixed signal system on chip is increasing. The proposed BIST scheme is developed to test the data converters, both DAC and ADC on chip as well as other analog IP modules depending on specification of design without/least affecting the architecture of actual design and without making use of any complex DSP circuitry. The concept of internet node access based testing of digital blocks is also used for dynamic parameter of DAC like offset voltage and gain error, monotonicity and linearity non-specific BIST scheme. Letter the digital control logic protion of SAR ADC is tested with scan-chain insertion and thus overall functionality of SRA ADC is verified. A simple comparison based method is also proposed for other type ADCs. For other anlog IPs, we propose IP-based testing where digital to analog converted test signals can be applied depending on specifications of IP design from vendor without affecting architecture of the design. The output from IPs are taken at different nodes and applied directly to ADC on chip. The digitized output response is then compared with expected response to test the functionality of the DUT and find out its deviation from desired value to achieve pre-defined level of accuracy. The design failing any of the sequence of afore-mentioned test is discarded faulty. The circuitry is designed and evaluated at schematic level using TSMC complementary metal oxide-semiconductor (CMOS) 0.5um technology.
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    Statistical co-analysis, robust optimization and diagnosis of USB 2.0 system for signal and power integrity
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Tripathi, Jai Narayan; Dubey, Rahul
    Signal Integrity (SI) and Power Integrity (PI) are the most critical issues as semiconductor industry is moving towards higher operational speeds. Signal integrity and power integrity are such issues that should be looked at system level rather than looking at active and passive networks separately. System level analysis becomes a necessity when the individual subsystems work according to specifications, and even after that complete system doesn't work well. System level signal integrity and power integrity problems for high speed serial links have been taken into account in this thesis. Serial links are being used more and more rather than parallel links due to lesser skew and lower pin counts. Specifically USB 2.0 IP is used for this thesis work, but the analysis is generic for all serial links. This thesis considers SI and PI as a dual and a common model is used which considers both SI and PI. A statistical co-analysis of SI and PI for high speed serial links is used, which can be used for a cost effective solution too. Statistical methods are used for efficient simulations and to extract maximum information contents in the least simulation combinations. Based on this co-analysis, the system is diagnosed or modified for better SI and PI. In the end, reflection gain concept is also taken in to account for the diagnosis of the system. All in all, USB 2.0 system is diagnosed for better SI and PI. System level robustness analysis of high speed serial links are taken into account with effect of external environment. A strong correlation between measured and simulated results is shown. A generic methodology for SI and PI for high speed serial links is presented with complete analysis of package, board, termination, squidd card, decoupling network etc..