M Tech Dissertations
Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3
Browse
7 results
Search Results
Item Open Access Analysis of charge injection in a MOS analog switch with impedance on source side(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Rao, D. Srinivas; Sen, SubhajitTurning off of a transistor introduces error voltage at the output of Sample and Hold circuits which are the key components of Analog to Digital Converters (ADCs) and hence limits their accuracy of performance in high switching applications. The error voltage at output is mainly caused because of charge injection due to the carriers released from the channel and due to coupling through gate-to diffusion overlap capacitances. Hence, in order to fully understand the behaviour of charge injection in the presence of source impedance, a device is modelled and simulated in Pisces. This thesis is about modelling of an N-type Metal Oxide Semiconductor (NMOS) device in Pisces Postmini Tool with a hold capacitor on drain side, so that it can be used as a CMOS Analog switch. The main aim is to analyze the trends in output error voltage in the presence of source resistance. The output error caused due to charge injection is examined as a function of different parameters like gate voltage fall time, source resistance, input voltage, substrate concentration etc. Test structures similar to the one modelled in Pisces is simulated in 0.18μm CMOS technology for the verification purpose. It is shown that the modelled and simulated results exhibit good trend agreement.Item Open Access High speed sample and hold circuit design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dwivedi, Varun Kumar; Parikh, Chetan D.Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its front-end component. In this thesis, the high speed sample and hold circuit has been designed, requiring low power as a front end block of pipeline analog to digital converter. In this work, architectures of sample and hold circuit are studied and issues which limit the performance of sample and hold circuits are discussed. A fully differential S/H circuit using bottom plate sampling is proposed. The circuit has been designed in order to meet the specification. Amplifiers are studied and folded-cascode amplifier is chosen as an optimum architecture for switch capacitor based sample and hold circuit. The proposed circuit is designed optimally in a 180 nm CMOS process, in the Cadence Spectre environment. The speed and power achieved are 125 MSPS, 6.8mW respectively.Item Open Access Built-in self test architecture for mixed signal systems(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Jain, Mahavir Rajmal; Mandal, Sushanta; Nagchoudhuri, DipankarBuilt-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and used for digital circuitry due to well defied fault models and advanced designs tools and techniques available. But with more analog circuitry being built on same platform with digital circuitry, the necessity for BIST architecture of mixed signal system on chip is increasing. The proposed BIST scheme is developed to test the data converters, both DAC and ADC on chip as well as other analog IP modules depending on specification of design without/least affecting the architecture of actual design and without making use of any complex DSP circuitry. The concept of internet node access based testing of digital blocks is also used for dynamic parameter of DAC like offset voltage and gain error, monotonicity and linearity non-specific BIST scheme. Letter the digital control logic protion of SAR ADC is tested with scan-chain insertion and thus overall functionality of SRA ADC is verified. A simple comparison based method is also proposed for other type ADCs. For other anlog IPs, we propose IP-based testing where digital to analog converted test signals can be applied depending on specifications of IP design from vendor without affecting architecture of the design. The output from IPs are taken at different nodes and applied directly to ADC on chip. The digitized output response is then compared with expected response to test the functionality of the DUT and find out its deviation from desired value to achieve pre-defined level of accuracy. The design failing any of the sequence of afore-mentioned test is discarded faulty. The circuitry is designed and evaluated at schematic level using TSMC complementary metal oxide-semiconductor (CMOS) 0.5um technology.Item Open Access Design of a high speed I/O buffer(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Rathore, Akhil; Parikh, Chetan D.In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. CML buffers achieves high speed due to low output voltage swing which reduces transition time. Presently CML buffers are designed with differential architecture and uses different bandwidth extension technique (inductive peaking, negative miller capacitance, active feedback) to increase the speed. At high frequency, input output coupling limits the bandwidth due to miller effect because of gate to drain capacitance. The proposed design incorporates the architecture which reduces miller effect, hence achieves high bandwidth. In this topology a source follower drives a common-gate stage which is an example of ‘unilateral’ amplifier, that is, one in which signal can flow only in one way over large bandwidths. It reduces unintended and undesired feedback. This CML buffer is designed for OC-192/STM-64 application to be used in limiting amplifier which is a critical block in optical system. OC-192/STM-64 works around 10Gbps.Item Open Access Adaptive biased switched capacitor filters(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Bajaj, Garima; Parikh, Chetan D.The demand from today’s handheld devices, such as laptop, ipod, cellphones is to have a long battery life with no compromises in speed. The devices dissipate power even in standby mode also. Op-amp is a major block in all these devices. Its application in these devices may be as an amplifier, filter, A/D or D/A convertor. In most of the cases the op-amp may be in standby mode with no input signal. Power dissipated in these standby periods is wasted, and this is of concern for two reasons. First, in battery powered equipment, supply power must be conserved to extend the battery life. Second, any power wasted in the circuit is dissipated in the active devices which mean that they operate at higher temperatures and thus have a greater chance of failure. So the point of major concern is to reduce power in standby modes, and to give high speed when the device is operating. This research work makes an attempt to design the most common application of Op-amp, a filter, such that it consumes low power with no compromise in speed. It ensures that the load capacitor of op-amp settles to the final value at a much faster speed, and at the same time consuming less power in stand by mode. The filter is designed for a cut off frequency of 100KHz at 2.5V in 0.18μm technology. The filter with a higher cut off frequency requires higher current and thus results in large power dissipation. The two Op-amps discussed, are proved and verified that they consume very less power for such a high cut off frequency.Item Open Access Tool to calculate the width and length of capacitor for switched-capacitor band pass filter(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Doshi, Kaushal J.; Nagchoudhuri, DipankarThe switched capacitor (SC) circuits find their applications in many fields. Due to their lower size at low frequencies, higher density can be achieved compared to active RC counterparts. Still there are nonlinerarities in SC circuits, many which are due to error in fabrication process. As will be explained later, the performance of SC circuits depends on capacitance ratios instead on absolute values; hence as designer, we are interested in matching the capacitance ratios rather than absolute values.This tool which we designed takes care that the width and length of the capacitors it gives as output, has area ratios and perimeter ratios equal for all capacitor pairs, thus taking care of the proper matching of all capacitor.
Item Open Access Design of CMOS voltage controlled oscillator for high tuning range(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Nayudu, Bharath Kumar; Gupta, SanjeevThe main objective of the work is to design a CMOS voltage controlled oscillator for higher tuning range. Today there is a great need for multi-standard wireless receivers in the wireless communications. A receiver is to be designed such that it receives data from the different frequency bands and standards. It is essential to design an oscillator to adhere to some of the standards like CDMA, GSM, GPRS and others. CMOS was the ideal choice for this work because of its low power consumption compared to other technologies and its immunity to the noise. In the design of the tank circuit, binary weighted capacitive array technique (BWCA), discrete variable inductor by using MOS switch and variable capacitor for continuous tuning have been used. By using all the above three techniques, a higher tuning range has been achieved.