Design and Implementation of 3-stage Low Power Interrupt Driven Processor using RISC-V ISA
| dc.accession.number | T00853 | |
| dc.classification.ddc | 005.3 KOS | |
| dc.contributor.advisor | Bhatt, Amit | |
| dc.contributor.author | Kosta, Ankur | |
| dc.date.accessioned | 2020-09-22T17:20:43Z | |
| dc.date.accessioned | 2025-06-28T10:28:04Z | |
| dc.date.available | 2023-02-16T17:20:43Z | |
| dc.date.issued | 2020 | |
| dc.degree | M. Tech | |
| dc.description.abstract | The hardware-software interface, incorporated in the Instruction set architecture (ISA), is arguably the most crucial interface in the computer system. An open ISA standard can help in increasing the innovation in microprocessor design and reduce the overall cost of the computer system. In this project, I present a Low power Interrupt-Driven 3-stage microprocessor using RISC-V ISA. RISC-V is a free and open ISA which is structured as a small base ISA with multiple optional extensions. The base ISA is very simple, making it appropriate for research and education purposes but, complete enough to be suitable for inexpensive, low power embedded systems. The optional extension makes it even more powerful ISA, which is suitable for general purpose and high-performance computing. | |
| dc.identifier.citation | Kosta, Ankur (2020). Design and Implementation of 3-stage Low Power Interrupt Driven Processor using RISC-V ISA. Dhirubhai Ambani Institute of Information and Communication Technology. vi, 17 p. (Acc.No: T00853) | |
| dc.identifier.uri | http://ir.daiict.ac.in/handle/123456789/931 | |
| dc.subject | RISC-V | = |
| dc.subject | Interrupt-Driven | |
| dc.subject | Low Power | = |
| dc.title | Design and Implementation of 3-stage Low Power Interrupt Driven Processor using RISC-V ISA | |
| dc.type | Dissertation |