Integrated capacitance to digital and resistance to digital converter

Abstract

The wide use of capacitive sensors to determine pressure, humidity, position, andconcentration etc, in wireless sensor networks has been reported readily. Majorityof the Capacitance to Digital converters reported till date use charge sharingor charge transfer methods to convert capacitance to voltage value. A fully digitalCapacitance to Digital Converter is presented. The proposed architecture isbased on the principle of iterative delay-chain discharge along with the idea of delaycomparison. Significant improvement in terms of measuring time and powerconsumption has been observed. The design comes up with a power consumptionof 54mW, conversion energy of 37pJ, resolution of 0.617pF, less measuringtime along with reduced complexity in the architecture in 0.18mm CMOS. Further,the CDC architecture is extended to function as Resistance to Digital Converterwhich exhibits a range of 30KW to 70KW with resolution of 130W.