Analysis of tracking distortion in bootstrapped gate MOSFET sample-hold circuits and a method for its minimization

Abstract

A theory for the analysis of tracking distortion using the Volterra series is developed for bootstrapped gate sample-hold circuits with arbitrary signal AC gain applied at the gate. It is shown that second (HD2) and third (HD3) harmonic distortion show zeroes (minima) with respect to bootstrap gain whose location depends upon gate and substrate bias. Furthermore, the HD2 minimum occurs when the body-effect is compensated by applying a gain equal to the subthreshold slope factor of the MOSFET. These results are verified by using simple physics-based strong-inversion and surface-potential models as well as the PSP compact model. The cases of distortion and phase-lag in the bootstrap gate path are also considered. Measured second harmonic distortion on a discrete prototype shows reasonable agreement against simulation results using extracted MOSFET model parameters.