Design and implementation of single electron transistor based 8X8 bit signed multipliers

Abstract

Single electron transistor (SET) has several advantages over CMOS such as it is highly scalable and has ultra-low power consumption. It has emerged as a promising technology to be used as a building blocks for next generation integrated circuit design. In this paper, prospective and efficient implementation of high speed, low power and extremely compact digital multipliers using SET is proposed for the first time. For effective analysis and comparison, three different 8-bit signed multipliers such as Baugh Wooley, Booth and Array multiplier have been designed and their simulation results are validated using the Cadence Virtuoso ADE tool. Performance comparison in terms of power and delay between SET and 16?nm CMOS is evaluated. From the simulation results, it is observed that multipliers based on SET outperforms its CMOS counterpart in all aspects. Considering above mentioned multipliers, SET based Booth multiplier design is having lowest power consumption of 1.41?�W and propagation delay of 6.09?ps as compared to 7.53?�W and 454.94?ps respectively for CMOS counterpart below.