Publications
Permanent URI for this collectionhttps://ir.daiict.ac.in/handle/123456789/32
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Publication Metadata only Reliability Assessment using Electrical and Mechanical Characterization of Stretchable Interconnects on Ultrathin Elastomer for Emerging Flexible Electronics System(IEEE, 10-07-2025) Bhatti, Gulafsha; Sharma, Rohit; Kumar, Mekala Girish; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, GandhinagarPublication Metadata only Essential Frequency Analysis for Stacked Cu-CNT Composite Cells of TSVs(IEEE, 04-03-2025) Kumar, Mekala Girish; Agrawal, Yash; Pulluri, Harish; Sharma, Rohit; DA-IICT, GandhinagarPublication Metadata only Explicit Analytical Model of Stretchable Interconnects for Flexible Electronics System(IEEE, 24-07-2025) Bhatti, Gulafsha; Kumar, Mekala Girish; Sharma, Rohit; Palaparthy, Vinay; Agrawal, Yash; DA-IICT, GandhinagarA printed circuit board (PCB) is one of the strong backbones to execute electronic system designs. Due to fast and reliable communication requirements between integrated circuit and other peripheral components over the PCB, there is a quest for the development of board-level designs and layouts. The advancement in technology has led to inventions from conventional rigid to flexible PCBs or flexible electronics (FE). The conformability of FE circuitry majorly depends upon the stretchable interconnects. An interconnect is the medium through which a signal is transmitted. The characteristic of stretchable interconnects is determined through their electrical and mechanical properties. The analytical model and parasitic extraction of the interconnect for rigid PCB structures have been widely explored earlier. However, the analytical formulation of the stretchable interconnect still remains a challenge and meagerly explored till date. Consequently, in this work, an explicit analytical model for the parasitic extraction of stretchable interconnects, viz., resistance (R), inductance (L), and capacitance (C), under stretching and bending effects has been novelly proposed. Five different interconnect materials have been considered for the analysis. The analytical model results have been validated with the ANSYS EDA tool. It is investigated that the proposed analytical model results are in very close agreement with the ANSYS results for all the considered cases.Publication Metadata only Neural Network-based Fast and Intelligent Signal Integrity Assessment Model for Emerging MWCNT Bundle On-Chip Interconnects in Integrated Circuit(Taylor & Francis, 26-02-2023) Bhatti, Gulafsha; Pathade, Takshashila; Agrawal, Yash; Palaparthy, Vinay; Gohel, Bakul; Parekh, Rutu; Kumar, Mekala Girish; DA-IICT, Gandhinagar; Gulafsha Bhatti (202021005); Takshashila Pathade (201621013)At nanometer technology nodes, the efficient signal integrity and performance assessment of vast on-chip interconnects are crucial and challenging. For a long time, copper (Cu) has been used as an interconnect material in integrated circuits (ICs). However, as heading towards lower technology nodes, Cu is becoming inadequate to satisfy the requirements for high-speed applications due to its physical limitations. To mitigate this issue, a multiwall carbon nanotube bundle (MWCNTB) is proven to be a better replacement for Cu. Hence, the current work innovatively focuses on modeling, analysis, and performance evaluation of MWCNTB interconnects at 32?nm technology nodes using various machine learning (ML) and neural network (NN) based techniques for signal integrity assessment and fast computation of on-chip interconnect design. Based on the results obtained by comparing the different performance parameters, it is envisaged that NN-based ADAM technique leads to the best-suited model. The developed model is fruitful in evaluating the output performance of the system, such as power-delay-product (PDP), performing parametric analysis, and predicting optimum input design parameters of the driver-interconnect-load (DIL) system. This work utilizes HSPICE and Python electronic design automation tools for its implementation.Publication Metadata only Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization(IEEE, 11-02-2021) Pathade, Takshashila; Kumar, Mekala Girish; Parekh, Rutu; Agrawal, Yash; Parekh, Rutu; Agrawal, Yash; DA-IICT, Gandhinagar; Pathade, Takshashila (201621013)The emerging VLSI technology and simultaneously highly dense packaging of devices and interconnects in nano-scale chips have prosperously enabled realization of system-on-chip designs and advanced high-performance computing applications. Concurrently, these have aggravated inevitable challenges in miniaturized integrated circuits (ICs). One of the main limiters in the performance of high-speed VLSI designs is the on-chip interconnects. The emerging graphene based mixed carbon nanotube bundle (MCNTB) interconnects have been investigated as one of the most suited and physically realizable on-chip structure. The present work focuses on utilization of MCNTB as nano-interconnects in the optimized way. Determining optimized placement of CNTs in MCNTB configuration is tedious, skilful task and meagerly explored till date. This has been innovatively taken-up in the current work. In the present paper, novel and efficient particle swarm optimization (PSO) technique is explored and innovatively incorporated to obtain optimal distribution of CNTs in a given rectangular area. The objective function considered for the design is to maximize the tube density. Several signal integrity analyses have been executed. The proposed optimized mixed CNT bundle structure is compared with other different configurations of CNT bundle structures. It is analyzed that the proposed optimized MCNTB configuration produces highly favorable results and is apt suitable for futuristic nano IC designs. The different modelling and performance analyses are performed using MATLAB, SPICE and ADS EDA tools.Publication Metadata only A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects(Elsevier, 01-12-2021) Kumar, Mekala Girish; Agrawal, Yash; Vobulapuram Kumar, Ramesh; Chandel, Rajeevan; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; Agrawal, Yash; DA-IICT, GandhinagarWith the feasibility to scale the devices and interconnects in highly sophisticated VLSI technology, the demand for high-speed and low-power�e-applications have also subsequently increased stupendously. Based on the applications and requirements, a VLSI system is operated in different modes as linear or sub-threshold. A unified analytical model for describing both these linear and sub-threshold modes is highly desirable. This has been innovatively presented in the current paper. Moreover, the futuristic and emerging mixed�carbon nanotube�bundle (MCB) as interconnects for both linear and sub-threshold region of operations has been considered. The essential signal integrity analysis comprising of several�crosstalk�effects such as associated�transient response, delay and power have been analyzed. To evaluate this, analytical model is formulated and proposed using accurate unconditionally-stable finite-difference time-domain (USFDTD) technique. Utilizing the proposed model, it is investigated that linear mode of operation is good for realizing high-speed systems while sub-threshold is a preferable operation for applications targeted for low-power. Comprehensively, it is envisaged that the average power-delay-product in MCB interconnects operating in sub-threshold region is low and reduced by 74% compared to corresponding linear region of operation. Also, it is demonstrated that the proposed unified USFDTD based model for MCB interconnects operating in different modes of operation is stable and not constricted by the Courant condition. At maximum allowable�time step, the proposed model is nearly 10 and 25 times faster than the conventional FDTD analytical and HSPICE simulation models, respectively. The results reveal that USFDTD technique provides better accuracy than the FDTD technique. The different performance analyses are performed at 22�nm technology node.