Theses and Dissertations

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Subject: search.filters.subject.Fourier transformations

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    Design and implementation of 128-point fixed point streaming FFT processor for OFDM based communication system
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Verma, Sunil Kumar; Dubey, Rahul
    Fast Fourier Transform (FFT) processors are today one of the most important blocks in communication systems. They are used in every communication system from broadband to 3G and digital TV to Radio LANs. This master’s thesis project deals with the pipelined, radix-2 algorithmic exploration and the hardware solution for the FFT processor with the FFT size of 2N points, the selection of the scaling schemes based on application requirement is discussed. The designed architecture is functionally verified in Simulink® and the Xilinx® ISE simulator. How to encapsulate the C++ coded algorithms or functions into the Simulink. This FFT processor is used in OFDM based BPSK modulated communication system for the WHD WVAN standard at the Low Rate Physical (LRP) lay. This thesis project presents the design of the 128 point fixed–point F streaming processor. The final architecture used is the SDF (single path with delay feedback) that implements the radix-2 FFT algorithm. Since the FFT processor can’t be used standalone, so in this thesis it is employed in an OFDM Transmitter and the performance is measured for SNR over a range of PAPRs. The goal of this report is to outline the knowledge gained during the master’s thesis project, to describe a design methodology for the fixed point pipelined FFT processors, the scaling choices and how to encapsulate the existing C code into the Simulink environment to measure the performance of fixed-point systems.
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    Pulse shaping design for PAPR reduction in OFDM
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Jain, Akansha; Vijaykumar, Chakka
    Future mobile communications systems reaching for ever increasing data rates require higher bandwidths than those typical used in todays cellular systems. By going to higher bandwidth the (for low bandwidth) at fading radio channel becomes frequency selective and time dispersive. Due to its inherent robustness against time dispersion Orthogonal Frequency Division Multiplex (OFDM) is an attractive candidate for such future mobile communication systems. OFDM partitions he available bandwidth into many subchannels with much lower bandwidth. Such a narrowband subchannel experiences now almost at fading channel. However, one potential drawback with OFDM modulation is the high Peak to Average power Ratio (PAPR) of the transmitted signal: The signal transmitted by the OFDM system is the superposition of all signals transmitted in the narrowband subchannels. The transmit signal has then due to the central limit theorem a Gaussian distribution leading to high peak values compared to the average power. system design not taking this into account will have a high clip rate. Each signal sample that is beyond the saturation limit of the power amplier suersither clipping to this limit value or other non- linear distortion, both creating additional bit errors in the receiver. One possibility to avoid clipping is to design he system for very high signal peaks. However, this approach leads to very high power consumption (since the power amplifier must have high supply rails) and also complex power amplifiers. The preferred solution is therefore to apply digital signal processing that reduces such high peak values in the transmitted signal thus voiding clipping. These methods are commonly referred to as PAPR reduction. APR reduction methods can be categorized into transparent methods here the receiver is not aware of the reduction scheme applied by the transmitter and on-transparent methods where the receiver needs to know the PAPR algorithm applied by the transmitter. This master thesis would focus on transparent PAPR reduction algorithms. The pulse shaping mechanism is used to reduce PAPR. he ct is analyzed in terms of BER.
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    High-speed 512-point FFT single-chip processor architecture
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sinha, Ajay Kumar; Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar
    This thesis present a fully parallel novel fixed point 16-bit word width 512 point FFT processor architecture. The 512 point FFT is realized by decomposing it into three 8 point FFT units. This approach reduces the number of required complex multiplication compared to the conventional radix-2 512 point FFT algorithm. It uses an ROM unit for storing the twiddle factor. The proposed architecture is designed in XILINX 8.2i using Verilog and it is functionally verified with the MATLAB. The floorplanning and timing estimation of each basic module of the proposed architecture is done based on the macro element at 0.25 CMOS technology. The core area of this chip is 99.02 mm2. The processor compute one parallel to parallel (i.e. when all input data are available in parallel and all output data are generated in parallel) 512-point FFT computation in 422 clock pulse in 4.69sec at 90 MHz operation.
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    ASIC implementation of discrete fourier transform processing module
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Navneet; Dubey, Rahul
    This work presents the design and ASIC implementation of Discrete Fourier Transform Processing Module. The performance of designed DFT processing module is better than radix-2 and radix-4 FFT algorithms, and is comparable to Split radix FFT algorithm, in terms of computational requirements. Different architectures are proposed for DFT processing module, and their comparative analysis is done. ASIC implementation of Discrete Fourier Transform processing module includes, its modelling using Verilog HDL, gate level synthesis of the modelled design and physical synthesis of netlist generated by gate level synthesis. The functionality of Design after physical synthesis is verified. Designed DFT processing module is retargetable and can be used as an IP.