Theses and Dissertations
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Item Open Access Design of a Real Time Low Power Interrupt Driven Processor With Fair Scheduling(Dhirubhai Ambani Institute of Information and Communication Technology, 2017) Shrotriya, Tushin; Bhatt, Amit"Recent times have seen a considerable amount of growth in the processor industry. The design of a processor is mainly focussed on two aspects namely, high performance or low power. While some high-end applications require greater performance, there are areas such as home automation where the focus is put on making a low cost, low power processor so that it can be used as an aid in our day-to-day activities such as home security, lighting or temperature control etc. In such applications, some tasks take precedence over the other tasks and must be completed within a specified amount of time. This leads to the requirement for a real time processor. Also, as different tasks have their respective priorities, the lower priority tasks might not get a chance to finish if we use the conventional priority based scheduling algorithms. Thus, we have devised a fair algorithm which increases the chance of lower priority tasks to finish. This is implemented by the interrupt controller unit designed along with the processor (core). As a complete system is to be made, there needs to be a medium which facilitates the communication between the sensors and the processor. This is accomplished by the implementation ofWishbone bus. To make our processor low power, we have made a wake-up interrupt controller (WIC) unit that switches all the other units off whenever there are no interrupts to be served. Thus, a complete System-on- Chip (SoC) was designed with these modules to implement a real time and low power interrupt driven processor which provides a fair chance to the lower priority interrupts while providing deterministic response to the time critical high priority interrupts. The SoC was designed using Verilog language. The front-end synthesis is performed using Cadence RTL compiler. The technology library used for the front-end analysis is Nangate (45nm)."Item Open Access Power reduction schemes in an interrupt driven processor based SoC(Dhirubhai Ambani Institute of Information and Communication Technology, 2016) Gupta, Shruti; Bhatt, AmitIn recent time, an impressive growth of personal computing devices like portabledesktops, multimedia products and wireless communication systems has beennoted. As the IoT industry has grown very fast, so is the need for low powerprocessor. When we talk about smart city or a smart room, the first thing is thatthe data will be coming from sensors. Processor operating on the sensor datamust be quick to respond and low power, so as to remove the havoc of replacingbattery. To meet the intensive computational requirements and complex real timefunctions, it has become important to integrate traditional microprocessor withmemories and peripherals on a single chip, which is known as System-on-Chip(SoC). For any SoC targeted for real time application, two most important thingsare: Power Management and Deterministic response.Power consumption consists of two parts: Dynamic Power and Leakage Power.Initially dynamic power was dominating in total power consumption but with thetechnology node shrinking and devices becoming smaller in size, leakage powerhas become dominant part of power consumption. There are various techniquesdevised for reducing leakage power. An interrupt driven three-stage processoris designed using verilog, where sensor data acts as interrupt and deterministicexception response is done with the help of a module named Nested VectoredInterrupt Controller (NVIC).In this thesis power optimization is done at system, architecture and technologylevels. The thesis is mainly concentrated on power shut off (PSO) techniquewhich is implemented at system level and is most effective to reduce the leakagepower. It includes shutting off modules in design which are going to be idlefor some time. With the increase in complexity of design, PSO implementationalso becomes difficult to implement. It is implemented using the Common PowerFormat (CPF) or Unified Power Format (UPF). Here, CPF has been used to implementPSO and is done at three different designs levels; on ALU, interrupt drivenprocessor and the System on Chip (SoC). Techniques like clock gating, avoidingcells and library of slow PVT are used to further reduce leakage power along withPSO.Item Open Access Statistical delay modeling and analysis for system on chip(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Patel, Jay; Nagchoudhuri, DipankarIt is seen that designing using conventional methodologies in Deep Sub Micron geometries, at times, ends up in very pessimistic design and less yield. This is because, today’s tools don’t consider statistical variation of parameters in the fabrication process. IC manufacturer can give probability distribution of such parameters. Using those distributions the tool to be designed will give the probability distribution for delays and slacks. A probabilistic estimation can be made about design functioning in deep sub micron geometries. The delays will have probability distributions based on the parameter variations. These distributions can be found using the way of SPICE simulations. But when circuit complexity increases, these simulations will take a lot of time and it is not the suitable way for large designs. A quick and efficient model has been developed based on MOSFET characteristics. Moreover, a statistical delay model for propagation delay of a gate has also been worked out. Also new methodology and implementation scheme is proposed.