Theses and Dissertations

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    Finding Proxy For Human Evaluation Re-evaluating the evaluation of news summarization
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2022) Ranpara, Tarang J.; Majumder, Prasenjit
    Engaging human annotators to evaluate every summary in a content summarization system is not feasible. Automatic evaluation metrics act as a proxy for human evaluation. A high correlation with human evaluation determines the effectiveness of a given metric. This thesis compares 40 different evaluation metrics with human judgments in terms of correlation and investigates whether the contextual similarity based metrics are better than lexical overlap based metrics, i.e., ROUGE score. The comparison shows that contextual similarity based metrics have a high correlation with human judgments than lexical overlap based metrics. Thus, such metrics can act as a good proxy for human judgment.
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    Low-power pipelined crypto-core using a backup flip-flop
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Patel, Sagar; Bhatt, Amit
    With increasing clock frequencies, power-aware computing has become a critical concern in the VLSI design. One of the most effective and widely used method for lowering the power is DVS (Dynamic Voltage Scaling), which is the basic idea behind making low-power pipeline. Total power consumed by the system consists of dynamic power and leakage power. They both depend on the supply voltage, as they decrease with a decrement in supply voltage. But lower supply voltage causes more delays at the gate level, as there is less amount of voltage to charge the output capacitance of a gate. These delays can cause timing violations in the critical path. So, if the supply voltage of the system could be reduced somehow without affecting the overall functionality of the system, great power saving can be achieved. Usual DVS techniques need to have margin for process and temperature variations or any local variations. These voltage margins make the design less efficient in terms of power. Backup flip-flop can be used for the critical path, which operates on the different clock, delayed by some specific amount of delay. It covers the effect of voltage reduction as well as process and temperature variations with all local variation effects, which can affect delay in any manner. If there is any error, it needs to be corrected for a correct functionality of the system. Error correction mechanism and the architectural overview of AES crypto-core is also discussed, as it is the chosen design on which this concept would be implemented. Similar concept has been successfully tried out on Alpha processor with satisfactory result. All the simulations shown are post-synthesis or post-route simulations so that they reflect the approximated delays and timing checks of logical gates and interconnects. Simulations and synthesis were performed using Cadence NC-Launch and Encounter RTL Compiler respectively. ’Nangate Opencell Library’ with 45nm technology was used for the synthesis.
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    Path planning of data mule using responsible short circuit with steiner points
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Vora, Ankitkumar; Srivastava, Sanjay; Sunitha, V.
    We have studied the problem of data aggregation method in wireless sensor network using the data mule. In data mule approach, Data mule is the mobile entity which can collect the data from stationary sensor node in the network. Data mule approach significantly improves the network lifetime. Network lifetime is main concern while designing the application of sensor network because most of the time sensor nodes die due to power discharge. On the other hand Data mule approach increases the data latency compared to other existing methods. There is a trade-off between network lifetime and data latency. Data latency of the data mule can be minimized using the proper motion planning of the data mule. As part of the motion planning we have studied the path selection problem for data mule using the Responsible short circuit algorithm. Responsible short circuit algorithm finds the equivalent responsible edge for two or more consecutive edges of that path. Using the Steiner node placement at the overlap region of sensor node’s communication can further improve the path for the data mule. We have combined the Responsible short circuit algorithm with Steiner node placement and tested using the simulation on java technology. This combination significantly improves the path length compared to existing approaches. We have tested the Responsible short circuit without Steiner node algorithm and Responsible short circuit with Steiner node algorithm for Uniform node deployment as well as the Cluster node deployment. We also have thought about the hybrid approach of Clustering and data mule approach which can improve the path selected for data mule.
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    D-latch based low power memory design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Tripathi, Saurabh; Mishra, Biswajit
    Low power consumption is the main attraction of the digital circuit design in the Sub threshold region of operation. In this region of operation less energy is consumed for active operation and less leakage power is dissipated than higher voltage alternatives. As a trade-off circuits operate slowly because the supply voltage is less than the threshold voltage of the transistors. Sub-threshold operation is considered as an effective solution in designs where low power consumption is the prime concern and operating speed can be sacrificed. The sub-threshold systems need the same voltage level operated memory design. Also, the sub-threshold memory design must be robust in terms of SNM (signal to noise margin) as the operating supply voltage is few hundreds of millivolts depending on technology node. This demands the architecture that ensures the effective data read/write operation under all critical conditions. This research work mainly focuses on D-Latch based 128 Byte full custom memory array and memory controller design. Starting with different latch architectures’ minimum operating supply voltage comparison, the complete Byte addressable memory design flow including row/column decoder design, memory controller design has been discussed. The complete layout of the memory, performance results under an application and its different parameters have also been included in the report. All the design parameters and the simulation results are produced for 0.18μm process.