Theses and Dissertations

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    MMIC based high power transmit/receive and receive protection switches with integrated LNAs
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2019) Rao, Ch. V. Narasimha; Ghodgaonkar, Deepak K.
    The conventional high power microwave signal switching component is the Silicon/GaAs PIN diode, while the recently GaN pHEMT devices are being used for this application. GaAs FET, used as switching element as a PIN diode replacement, has the advantages of having fast switching speeds, simplified bias networks, monolithic compatibility, and lower power consumption driver circuitry. The major advantage of having a GaAs FET based high power T/R switch or protection switch is that other functionalities of Receiver can be integrated on to MMIC (Monolithic Microwave Integrated Circuit) making a multi-functional core-chip. However, the power performance of a FET is limited by its current-handling capability in its low-impedance state and by its breakdown voltage in its high-impedance state. In this thesis, various new and novel circuit architectures are presented for increasing the power handling capability of GaAs FET based switches, using low noise and low power processes, to enable the realization of high power T/R switch with integrated LNA or absorptive high power receive protection switch with integrated LNA. So developed technique is employed for designing high power GaN FET based switches to further increase the power handling capability, beyond that of individual GaN FET switch, and also integrating LNA using the same GaN process. On-the-chip current distributed architecture, for increasing the power handling capability, is proposed, analyzed and employed for realizing a GaAs MMIC 10W T/R switch with integrated LNA, employing 0.25-?m GaAs pHEMT process (PH25 of M/s UMS, France). The measured transmit loss, Noise Figure (NF) and receive path gain are 1.0 dB, 2.5 dB and 5.6 dB respectively over 9.3-9.9 GHz. Novel impedance transformation along with on-the-chip current distribution technique, for increasing the power handling capability and improving the receive path loss, is proposed, analyzed, and employed for designing a GaN MMIC 200W T/R switch with integrated LNA, using 0.25-?m GaN pHEMT process (GH25 of M/s UMS, France). The layout level electromagnetic and co-simulation results of this 200W pulsed power handling capability T/R switch with integrated LNA are 0.8 dB transmit path loss with 45 dB receive isolation, and 2.6 dB NF with 20 dB gain for the receive path over 3.1-3.3 GHz. Also, in this thesis, novel FET stacking along with on-the-chip current distributed architecture, for increasing the power handling capability and improving the receive path loss, is proposed, analyzed and employed for realizing a GaAs MMIC 20W absorptive receive protection switch with integrated LNA, employing 0.13-?m GaAs pHEMT process (D01PHS of M/s OMMIC, France). The measured results are protection up to 20W with 28 dB receive isolation, 2.9 dB NF and gain of 20 dB over 9.3-9.9 GHz. The constituent components required for designing T/R Switch with LNA, viz., high power quadrature hybrids, high power switches, LNAs are studied and design details presented. Various high power MMIC quadrature hybrid configurations have been studied and the design, analysis and simulation results of compact distributed high power MMIC spiral hybrid and high power MMIC quasi lumped impedance transforming hybrid are presented. MMIC GaAs and GaN HEMT based switch configurations have been studied vis-a-vis the power handling capability and novel techniques like on-the-chip current distributed architecture for increasing the power handling capability and techniques of impedance transformation and FET stacking techniques for improving the receive path insertion loss are proposed, analyzed and simulation results are presented. MMIC GaAs HEMT based Low Noise Amplifiers' configurations have been studied and X-band single stage and two-stage LNA design, simulations and measurement results are presented. MMIC GaN HEMT based S-band Low Noise Amplifier design and simulation results are presented.
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    ItemOpen Access
    Transaction based verification of discrete wavelet transform IP core using wishbone transactor
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Patel, Birenkumar; Dubey, Rahul
    Verification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debug at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. It does not require detailed test benches with large vector. Device under test (DUT) operates at a binary stimulus level(e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level (e.g. READ) and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The Discrete Wavelet Transform’s (DWT) Intellectual Property (IP) core is used as a DUT. DWT is implemented by Lifting scheme based Daubechies 9/7 filter. Lifting scheme has an advantage over conventional convolution method like time complexity of operation. Wishbone transactor is designed for verification of IP core. Whole system is verified on ZeBu emulator. The same Wishbone transactor is used for verification of different Wishbone compatible IP core.
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    Test methodology for prediction of analog performance parameters
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Akula, Sandeep; Nagchoudhuri, Dipankar
    Analog testing, the name itself signifies the detection of faults in analog circuits. The aim of this thesis is to increase the test effectiveness and work in the performance parameter space. There are many test methodologies which can detect the faults in the circuit under test (CUT), out of which the test methodologies which can determine CUT performance parameters resulting in enhanced test effectiveness are, predictive oscillation based test methodologies. To detect the catastrophic and parametric faults these methodologies are used. These test methodologies are preferred over other methodologies because the input test stimulus generation is not needed, which reduces the complexity if multiple inputs are applied to the circuit. These test techniques are implemented with prediction process using neural networks which will in turn increases the performance of the circuit under test. The thesis follows with the implementation of the techniques and understanding the methods to increase the test effectiveness. The design process is performed in CADENCE simulation tool with 180nm technology.
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    Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sesha Sai, Aduru Venkata Raghava; Parikh, Chetan D.
    In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor using a low-voltage gyrator topology with a feedback resistance, where feedback resistance is realized by a NMOS operating in triode region whose bias voltage tunes the inductance of the active inductor and hence the frequency of VCO. The simulation results shows that this VCO operates in a 1.19 GHz to 2.49 GHz , while consuming 1.09 mW from a 1.2V power supply. The VCO’s phase noise level is -86.9 dBc/Hz at 1 MHz offset from a 1.55 GHz carrier. The deviation of the phase noise is 11.5 dBc/Hz during this tuning range. All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology.
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    Design of low voltage high performance voltage controlled oscillator
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Ramesh, R; Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar
    In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback to achieve high performance in terms of phase noise and output voltage swing. It uses differential MOS varactors for frequency tuning due to which all low frequency noise such as flicker noise gets rejected. Inductor was designed and it was simulated in IE3D electromagnetic simulator to achieve good Quality factor. This VCO achieves a very low phase noise of -119dBc/Hz@1-MHz offset frequency, power consumption of 3.27mW, and tuning range of 6% .All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology