Theses and Dissertations

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    Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sesha Sai, Aduru Venkata Raghava; Parikh, Chetan D.
    In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor using a low-voltage gyrator topology with a feedback resistance, where feedback resistance is realized by a NMOS operating in triode region whose bias voltage tunes the inductance of the active inductor and hence the frequency of VCO. The simulation results shows that this VCO operates in a 1.19 GHz to 2.49 GHz , while consuming 1.09 mW from a 1.2V power supply. The VCO’s phase noise level is -86.9 dBc/Hz at 1 MHz offset from a 1.55 GHz carrier. The deviation of the phase noise is 11.5 dBc/Hz during this tuning range. All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology.
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    Novel local oscillator circuit for sub-harmonic mixer
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2005) Kishore, G. Pavan Krishna; Biswas, R. N.; Parikh, Chetan D.
    Direct Conversion RF transceiver is the enabling technique for the next generation cellular and personal communication devices striving for miniaturization, long life of battery and cost effectiveness. Existing techniques of Direct Conversion suffer from undesired carrier radiation from the receiver. This leads to distortion in the signal received by the users in the close proximity. The proposed transceiver design is an approach to address the discussed issue of carrier radiation. The existing systems use Sub Harmonic mixer to overcome this problem with a sinusoidal Local Oscillator (LO) running at half of the required carrier frequency. The W-CDMA systems which use QPSK modulation need eight phases of the LO, the generation of which consume large power due to the linear circuits used. The proposed design implements the octet phase LO using non-linear circuits. This leads to the significant improvement in terms of power consumption and area. The core work of the thesis involves designing and analysis of new circuit topology that uses CMOS inverter chain for generating the octet-phase trapezoidal LO, to drive the Sub Harmonic mixer. The improvements are possible through the reduced size of transistors used in inverter and its non-linear operation. Thorough analysis of the circuit is performed for both sinusoidal and trapezoidal LO. Competitive results are obtained from the analysis of the design in terms of conversion gain, carrier suppression and Input referred 3rd order Intercept Point (IIP3). The design is modified to make it robust for varying ambient temperatures using a junction diode. A two port model of the Sub Harmonic mixer is derived, which proves a non-sinusoidal LO can be used in place of sinusoidal.