M Tech Dissertations
Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3
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Item Open Access All Digital ECG Front End ASIC(2021) Joshi, Aaditya P.; Mishra, BiswajitThe research presents a continuation work of low power front-end digital electrocardiogram (ECG) acquisition system, designed and simulated (with Wilson Central Terminal ECG Database) using 0.18 mm CMOS technology model files at 0.5 V as the system is operated in sub-threshold region for low power consumption. Furthermore to detect the abnormalities in the heart, a digital code is generated by integrating time to digital converter (TDC) with the designed architecture and retracing of the ECG signal in MATLAB is carried out to check the accuracy of the previously designed architecture and of counter-based TDC which can be observed from the correlation between the retraced signal and the original signal. The correlation factor for the previously designed architecture observed for three patients of theWilson Central Terminal ECG Database is 0.9967, 0.9907, and 0.9881. The correlation factor for the counter-based TDC is 0.9913. In the ASIC design process, the layout of the basic sub-circuits of the architecture is implemented.Item Open Access FPGA implementation of an improved proportionate normalized least mean square (IPNLMS) algorithm(Dhirubhai Ambani Institute of Information and Communication Technology, 2018) Dubey, Deepankar; Das, Rajib Lochan; Mishra, BiswajitIn digital signal processing, estimation of an unknown signal is an important task,and in this context, different type of adaptive filters has been proposed to identifythese systems for on-line applications. Adaptive filters update its weight withthe help of certain algorithms. For real-time application, however, it is necessaryto implement these algorithms in hardware using the different basic mechanismof VLSI. Some algorithms with low computational complexity, like LMS, NLMShave been successfully implemented on FPGA.In this thesis, a popular sparse adaptive algorithm called IPNLMS algorithm,has been implemented on FPGA, Spartan 3E. In particular, on that FPGA board,we have designed 4-tap IPNLMS algorithm with maximum achievable frequencyof 21.85 MHz. Furthermore, this thesis proposes an architecture for 128-tapsIPNLMS algorithm, which is finally simulated on ISE design suite of Xilinx tool.The main feature of the proposed architecture is that it include minimum delay,and matrix multiplication is performed using minimum arithmetic operations,and scalar division has been implemented with suitable LUTs. It has also beenshown that the architecture is working at the frequency 40 MHz.Item Open Access Digital implementation of orthogonal frequency division multiplexing(Dhirubhai Ambani Institute of Information and Communication Technology, 2017) Bhanushali, Artiben; Pillutla, Laxminarayana; Bhatt, Amit"OFDM (Orthogonal Frequency Division Multiplexing) is the most important part of 4G and 5G technology which is adopted by many standards because of its various advantages. In this thesis, firstly prototype of OFDM system is designed according to 802.11a standard in MATLAB to check its performance and then to implement the same in Verilog using Xilinx ISE 14.4 design suite. FFT (Fast Fourier Transform) and IFFT (Inverse Fast Fourier Transform) are the most complex part of the design which are implemented using radix-2 algorithm. For channel estimation, scattered pilot arrangement is used to insert pilots at regular period in OFDM frame. At receiver side, least-square estimation is used to estimate the channel’s impulse response at known pilot tones. The system analysis is done using MATLAB-Verilog co-simulation in which Verilog transmitter and receiver are connected with MATLAB channel using testbench to generate the text files. This files are used as connecting platform between MATLAB and Xilinx. Performance of channel estimation at different number of multipath is observed which shows that the combination of time interpolation followed by frequency interpolation performs better over only frequency interpolation. In later part, BER (bit error rate) vs. SNR (signal to noise ratio) is analyzed for different number of multipath. From graphs, it is clearly denoted that, BER performance improves with respect to increase in SNR. Finally, fixed point and floating point comparison is carried out which depicts that fixed point system implemented in Verilog performs almost similar to the floating point implementation done in MATLAB."Item Open Access Forward error correction for software defined radio based on FPGA(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Agrawal, Amit H.; Dubey, RahulIn digital communication, the signal to noise ratio (SNR) of the channel is one of the major limitations on the operating performance. Solution in terms of coded data and errorcorrecting code has been introduced to improve the performance. Forward error correction technique with Convolution encoding and Viterbi decoding has been introduced here for this purpose. A Convolution encoder and Viterbi decoder of code rate 1/2, constraint length (K) of 7, 8 & 9 has been designed using Verilog HDL and incorporated with our application Software defined radio using black box in MATLAB Simulink. It is important to improve the performance and reduce the power and area of the decoder. In this project, Viterbi decoder adopted the Process Element (PE) technique which made it easy to adjust the throughput of the decoder by increasing or decreasing the number of PE. By the method of Same Address Write Back (SAWB), the number of registers reduced to half in contrast with the method of ping-pong.Item Open Access Broadband spectrum estimation using cascaded integrator comb filter(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Panarwala, Riyazahmed A.; Chakka, VijaykumarSpectrum estimation using different type of lters is a broad area of research nowadays. In this work, Cascaded Integrator Comb (CIC) lter based narrowband spectrum estimation and CIC band pass lter is presented. Then the broadband spectrum estimation is presented using CIC lters as well as Modied CIC lters with and without white noise. In eigen based methods, eigendecomposition of the autocorrelation matrix is to be obtained. This is a very complex and time consuming procedure while in CIC lter based methods only two additions are required, which signicantly reduces the complexity of the algorithm regardless of the factor M. Complexity based comparison is presented between CIC lter, Modied CIC filter based narrowband estimation and eigenbased frequency estimation methods. All the programs are written in MATLAB.Item Open Access Transmultiplexer design using different filters(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Shiyani, Bhavin R.; Chakka, VijaykumarTransmultiplexer is one of the applications of Filter banks, which is used to transmit many signals simultaneously through a single channel and so that to separate at receiving end. Design of transmultiplexer using prototype filters (low pass filters and band pass filters) has been studied and analysed with respect to complexity. Transmultiplexer design using complexity efficient polyphase structure has been studied and analysed in this thesis. In this thesis, different complexity efficient structures better than polyphase using CIC based structure, multistage CIC based structure, two stage CIC based decimator and multistage CIC based structure with compensator have been proposed. Performances of proposed structures are analysed (analysis of pass-band fluctuation, stop-band attenuation of each filter in transmultiplexer) in MATLAB environment with different classes of input like speech and image. This thesis also considers complexity of proposed structures.