M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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2007 - 20102

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Subject: search.filters.subject.Electronic apparatus and appliances

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    Transaction based verification of discrete wavelet transform IP core using wishbone transactor
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Patel, Birenkumar; Dubey, Rahul
    Verification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debug at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. It does not require detailed test benches with large vector. Device under test (DUT) operates at a binary stimulus level(e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level (e.g. READ) and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The Discrete Wavelet Transform’s (DWT) Intellectual Property (IP) core is used as a DUT. DWT is implemented by Lifting scheme based Daubechies 9/7 filter. Lifting scheme has an advantage over conventional convolution method like time complexity of operation. Wishbone transactor is designed for verification of IP core. Whole system is verified on ZeBu emulator. The same Wishbone transactor is used for verification of different Wishbone compatible IP core.
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    ItemOpen Access
    Low power improved full scan BIST
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Parashar, Umesh; Nagchoudhuri, Dipankar
    Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that influence the heat dissipation during test. This thesis presents a scan-based BIST scheme that reduces switching activity (SA) in the circuit under test (CUT) and test application time without compromising in fault coverage (FC). The proposed BIST scheme is based on combined BIST approach (combining both test-per-scan and test-per-clock test methodologies), two different functional lengths during scan, and a low transition random test pattern generator (LT-RTPG) as TPG. It takes optimal advantage of three techniques and reaches desired FC faster with a significant reduction in switching activity. Experiments conducted on different ISCAS’89 benchmark circuits report up to 24% reduction in SA and up to 80% reduction in the test length. The register transfer level (RTL) implementation of the proposed BIST is done on a 4-bit sequential multiplier circuit (for 90nm technology; Spartan-3 FPGA) to validate effectiveness of the proposed BIST under constraints of supply voltage, glitches, and technology parameters (for 90nm). Experimental results show that proposed BIST achieves 13.75% reduction in the average power dissipation compared to LFSR based BIST.