M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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  • ItemOpen Access
    Reduction of power using innovative Clock Gating and Multi Vth techniques in digital design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Sharma, Dushyant Kumar; Bhatt, Amit
    Low power is one of the most important issues in today’s ASIC (Application Specific Integrated Circuit) design. As the transistors scale down, power density becomes high and there is immediate need of reduction in power. There are different techniques available for reduction of power like Operand isolation (OI), Clock Gating (CG) and Multi Vth Library Utilization (MVLU). In this report, we present two approaches for power reduction. The first approach gives two algorithms that show how power and performance matrix is improved compared to conventional MVLU technique. In the second approach, it shows the implementation of constrained fanout clock gating and its benefits over conventional clock gating techniques in ASIC design methodology. This report also presents two analyses. The first analysis shows how the design metrics area, power and performance change due to different techniques of low power (Operand Isolation, Clock Gating and Multi Vth Cell Utilization). The second analysis demonstrates the effect of different CG cells in design and presents how the same design metrics are affected for each CG cell. There are two variations in each CG cell, one is with Reset and the other is without Reset. In this report, we also demonstrate how the design metrics are affected by insertion of Reset signal in each CG cell
  • ItemOpen Access
    Design of row decoder for redundant memory cell (SRAM)
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Mishra, Ashwini Kumar; Nagchoudhuri, Dipankar
    In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory array. The proposed circuit increases the yield and reliability with some loss in speed and overhead in terms of chip area. The circuit designed can test the design whenever a command to test is issued and it will detect and store the faults. Control Circuit designed, checks whether the given address of the memory operation is correct or not. If the address is faulty it replaces the faulty address with the spare address available in the chip. The existing control mechanism to replace faulty cell in a row replaces the cell bit by bit. But the design here instead of replacing the bit wise cells replaces the entire row containing the faulty cell. This architecture is more useful when there are more faulty cells in a single row. The row decoder is optimally implemented to reduce the time to access the data from memory. The operating voltage for the design is 3V. Layout, Simulation of testing circuit and redundant circuit with row decoder has been designed in CADENCE tool for .18μm technology. This Row decoder is working with 2.5GHz frequency.
  • ItemOpen Access
    High speed sample and hold circuit design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dwivedi, Varun Kumar; Parikh, Chetan D.
    Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its front-end component. In this thesis, the high speed sample and hold circuit has been designed, requiring low power as a front end block of pipeline analog to digital converter. In this work, architectures of sample and hold circuit are studied and issues which limit the performance of sample and hold circuits are discussed. A fully differential S/H circuit using bottom plate sampling is proposed. The circuit has been designed in order to meet the specification. Amplifiers are studied and folded-cascode amplifier is chosen as an optimum architecture for switch capacitor based sample and hold circuit. The proposed circuit is designed optimally in a 180 nm CMOS process, in the Cadence Spectre environment. The speed and power achieved are 125 MSPS, 6.8mW respectively.