Search Results

Now showing 1 - 4 of 4

Open Access
Realization of FPGA based digital controller
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Patel, Amit; Dubey, Rahul
Field Programmable Gate Array (FPGA) can be used to enhance the efficiency and the flexibility of digital controller. FPGA implementation of digital controllers leads to real time realizations with small size and high speed. Also it offers advantages such as complex functionality, fast computation, and low power consumption for high volume production. This thesis presents realization of FPGA based speed control of brushless dc (BLDC) motor - a real time application. The construction and the operation of the BLDC motor are described. The different control strategies for speed controller and digital pulse width modulation (PWM) control technique are implemented and tested on BLDC motor. Also their performance is evaluated. Proportional Integral (PI) controller and Fuzzy Logic Controller (FLC) are implemented in FPGA as a digital controller. The PI controller is governed by the values of proportional gain and integral gain, while FLC behaves in much similar way as human controls the system. Logics of both controllers: PI controller and fuzzy logic controller are written in High Description Language (HDL). The performance of the PI controller is better than the fuzzy logic controller in case of the complete known plant.
Open Access
Transaction based verification of discrete wavelet transform IP core using wishbone transactor
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Patel, Birenkumar; Dubey, Rahul
Verification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debug at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. It does not require detailed test benches with large vector. Device under test (DUT) operates at a binary stimulus level(e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level (e.g. READ) and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The Discrete Wavelet Transform’s (DWT) Intellectual Property (IP) core is used as a DUT. DWT is implemented by Lifting scheme based Daubechies 9/7 filter. Lifting scheme has an advantage over conventional convolution method like time complexity of operation. Wishbone transactor is designed for verification of IP core. Whole system is verified on ZeBu emulator. The same Wishbone transactor is used for verification of different Wishbone compatible IP core.
Open Access
Design of a high speed I/O buffer
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Rathore, Akhil; Parikh, Chetan D.
In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. CML buffers achieves high speed due to low output voltage swing which reduces transition time. Presently CML buffers are designed with differential architecture and uses different bandwidth extension technique (inductive peaking, negative miller capacitance, active feedback) to increase the speed. At high frequency, input output coupling limits the bandwidth due to miller effect because of gate to drain capacitance. The proposed design incorporates the architecture which reduces miller effect, hence achieves high bandwidth. In this topology a source follower drives a common-gate stage which is an example of ‘unilateral’ amplifier, that is, one in which signal can flow only in one way over large bandwidths. It reduces unintended and undesired feedback. This CML buffer is designed for OC-192/STM-64 application to be used in limiting amplifier which is a critical block in optical system. OC-192/STM-64 works around 10Gbps.
Open Access
Design of a CMOS variable gain amplifier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Verma, Vivek; Parikh, Chetan D.
In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new techniques to design analog circuits that can operate at lower supply voltages with desired performances. Another challenge for designer is to design a circuit with less power consumption while maintaining desired performance. In this thesis, a CMOS variable gain amplifier is designed to target above challenges. A fully differential, CMOS variable gain amplifier (VGA) has been designed for a 1.2- volt, low-power, 57-dB dynamic range, and high bandwidth. The VGA comprises of a control circuit, variable gain stages with common-mode feedback circuit. The gain of the VGA varies dB-linearly from -32 to 25 dB with respect to the control voltage, VC. Proposed VGA uses common-mode feedback (CMFB) circuit to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode range (ICMR) requirement and output swing of the VGA. The proposed VGA uses capacitive neutralization technique to achieve high bandwidth operation. This VGA draws 1.25 mA current from a 1.2 V supply. The 3-dB bandwidth varies from 110 MHZ (at 25 dB gain) to 3828 MHz (at -32 dB gain). The proposed VGA is simulated for 0.18μm CMOS technology in LT-Spice with BSIM3V3 model.

M Tech Dissertations

Browse

Filters

Settings

Sort By

Results per page

Search Results