M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Circuit Architecture

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    Low-power pipelined crypto-core using a backup flip-flop
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Patel, Sagar; Bhatt, Amit
    With increasing clock frequencies, power-aware computing has become a critical concern in the VLSI design. One of the most effective and widely used method for lowering the power is DVS (Dynamic Voltage Scaling), which is the basic idea behind making low-power pipeline. Total power consumed by the system consists of dynamic power and leakage power. They both depend on the supply voltage, as they decrease with a decrement in supply voltage. But lower supply voltage causes more delays at the gate level, as there is less amount of voltage to charge the output capacitance of a gate. These delays can cause timing violations in the critical path. So, if the supply voltage of the system could be reduced somehow without affecting the overall functionality of the system, great power saving can be achieved. Usual DVS techniques need to have margin for process and temperature variations or any local variations. These voltage margins make the design less efficient in terms of power. Backup flip-flop can be used for the critical path, which operates on the different clock, delayed by some specific amount of delay. It covers the effect of voltage reduction as well as process and temperature variations with all local variation effects, which can affect delay in any manner. If there is any error, it needs to be corrected for a correct functionality of the system. Error correction mechanism and the architectural overview of AES crypto-core is also discussed, as it is the chosen design on which this concept would be implemented. Similar concept has been successfully tried out on Alpha processor with satisfactory result. All the simulations shown are post-synthesis or post-route simulations so that they reflect the approximated delays and timing checks of logical gates and interconnects. Simulations and synthesis were performed using Cadence NC-Launch and Encounter RTL Compiler respectively. ’Nangate Opencell Library’ with 45nm technology was used for the synthesis.
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    Path planning of data mule using responsible short circuit with steiner points
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Vora, Ankitkumar; Srivastava, Sanjay; Sunitha, V.
    We have studied the problem of data aggregation method in wireless sensor network using the data mule. In data mule approach, Data mule is the mobile entity which can collect the data from stationary sensor node in the network. Data mule approach significantly improves the network lifetime. Network lifetime is main concern while designing the application of sensor network because most of the time sensor nodes die due to power discharge. On the other hand Data mule approach increases the data latency compared to other existing methods. There is a trade-off between network lifetime and data latency. Data latency of the data mule can be minimized using the proper motion planning of the data mule. As part of the motion planning we have studied the path selection problem for data mule using the Responsible short circuit algorithm. Responsible short circuit algorithm finds the equivalent responsible edge for two or more consecutive edges of that path. Using the Steiner node placement at the overlap region of sensor node’s communication can further improve the path for the data mule. We have combined the Responsible short circuit algorithm with Steiner node placement and tested using the simulation on java technology. This combination significantly improves the path length compared to existing approaches. We have tested the Responsible short circuit without Steiner node algorithm and Responsible short circuit with Steiner node algorithm for Uniform node deployment as well as the Cluster node deployment. We also have thought about the hybrid approach of Clustering and data mule approach which can improve the path selected for data mule.
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    Performance enhancement of a pipelined architecture using backup FF
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Singh, Shikha; Bhatt, Amit
    Commonly used devices like computers and mobile phones demand faster processors. These devices need to live up to the ever growing demand of consumers for performance. Special techniques like Pipelining and Superscalar Architecture increase the performance of processors at the cost of hardware. When using a pipelined architecture, the maximum frequency of operation and hence performance is limited by the longest path between two consecutive Flip Flops, also called the critical path. In designs where the critical path is rarely used, the frequency of operation can be safely increased by employing mechanisms that correct the error introduced if the critical path is taken. One such mechanism using Backup Flip Flop has been discussed and implemented in this dissertation. Problems like Metastability have been analyzed and resolved.