M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

Browse

Filters

20082

Settings

Subject: search.filters.subject.Bipolar integrated circuits

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    ItemOpen Access
    Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Ranjith, P; Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar
    This thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. Different logic families have been studied and Complementary Pass-transistor Adiabatic Logic (CPAL) is chosen to implement an adiabatic carry save multiplier as it gives less energy dissipation per cycle than other logic families at higher load capacitances and higher loads. The power clock is designed for CPAL which requires four phase trapezoidal waveform. An 8-bit carry save multiplier is designed which is used as load to clock generation circuit. The clock generator consumes equal energy per cycle at all frequencies. The control logic required for clock generation circuit is also simple to implement. Conversion efficiency of the order of 10% is obtained for an equivalent load capacitance of 2pF. The simulations are done using LT spice in 0.25μm TSMC technology. Layouts are drawn in MAGIC 7.1.
  • Thumbnail Image
    ItemOpen Access
    Design of voltage reference circuits
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Panchal, Bhavi; Parikh, Chetan D.
    Shrinking device dimensions in advancing CMOS technologies require lower supply voltages to ensure device reliability. As a result, analog circuit designers are faced with many challenges in finding new ways to build analog circuits that can operate at lower supply voltages while maintaining performance. Bandgap references are subject to these head-room problems especially when the required supply voltage approaches the bandgap voltage of silicon. However, the bandgap reference working with a low supply voltage often has a higher temperature coefficient than that of a traditional bandgap reference. This has resulted in the development of new temperature-compensated techniques. Piecewise linear curvature correction method is simple yet robust technique which was previously available in bipolar technology. This research work describes a Novel CMOS bandgap reference which uses piecewise-linear curvature compensation scheme for second order correction. In standard 0.18μm CMOS process, the reference, with 1.8 V supply produces an output of about 928 mV, which varies by 160 μV from -25 °C to 150°C. It dissipates 150 μW and has a DC PSRR of -46 dB.