M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Analog circuit design

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    Particle swarm optimization based synthesis of analog circuits using neural network performance macromodels
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Saxena, Neha; Mandal, Sushanta Kumar
    This thesis presents an efficient an fast synthesis procedure for an analog circuit. The proposed synthesis procedure used artificial neural network (ANN) models in combination with particle swarm optimizer. ANN has been used to develop macro-models for SPICE simulated data of analog circuit which takes transistor sizes as input and produced circuit specification as output in negligible time. The particle swarm optimizer explore the specfied design space and generates transistor sizes as potential solutions. Several synthesis results are presented which show good accuracy with respect to SPICE simulations. Since the proposed procedure does not require an SPICE simulation in the synthesis loop, it substantially reduces the design time in circuit design optimization.
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    Implementation of constant gm CMOS op-amp input stage using overlapping of transition region at 0.18 um technology
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Singh, Ram Sahay; Parikh, Chetan D.
    Operational amplifier is the backbone of most of analog circuit design. For low voltage applications, op-amp should have a rail-to-rail common mode input voltage. This report describes the implementation of a constant gm rail-to-rail CMOS op-amp using complementary input pairs, at 0.18µm MOS technology. The concept used to make the input transconductance (gm) constant is the overlapping of transition regions of n-pair and p-pair tail transistors using a DC level shifter [2]. A constant gm input stage insures a uniform frequency response for the entire common mode input range. It also improves the Common Mode Rejection Ratio (CMRR). The results of the designed op-amp show that it has a rail-to-rail input common mode range and a rail-to-rail output voltage swing. For rail-to-rail output voltage swing a Class AB output stage is used. Layout of the chosen architecture is made using 0.18µm technology. Comparisons of pre-layout and post-layout simulation results are done.