M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.ASIC

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    ASIC implementation of a pipelined bitrapezoidal architecture for discrete covariance kalman filter
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Agarwal, Vaibhav; Dubey, Rahul
    This work presents, the complete ASIC implementation of Discrete Covariance Kalman ¯lter, on a Parallel and Pipelined Bitrapezoidal Systolic Array architecture. The Kalman Filter equations are mapped on the designed architecture. This mapping requires, decomposing the overall equations, to calculate the Schur's complement, using Faddeev's algorithm. This facilitates an approach, to avoid the iterative process of calculation of matrix inverse. The designed Parallel and Pipelined architecture caters to high speed applications, by computing the single iteration of the filter in just 6 steps, each step individually taking only O(n) clock cycles. Further the processing efficiency is increased, by computing equations of O(n3) complexity in just O(n2) complexity only, where n is the order of the filter. Other unique feature of the designed architecture includes, increased robustness to rounding errors and resolving the reiterative Data input problem. The ASIC implementation was done by, Modelling the architecture using Verilog HDL,its Functional Verification was done, Logic Synthesis was done on Cadence RC 5:2 Synthesizer and Physical Synthesis on Cadence SOC Encounter. The implementation methodology presented for logic and physical synthesis resulted in efficient implementation of architecture in silicon. The design was mapped to target technology of 180nm and the synthesis results were analyzed. Physical synthesis was carried out for the same technology and the design gives final timing closure for 50MHz, which is quite high for a compute intensive algorithm like Kalman filter.
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    ASIC implementation of discrete fourier transform processing module
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Navneet; Dubey, Rahul
    This work presents the design and ASIC implementation of Discrete Fourier Transform Processing Module. The performance of designed DFT processing module is better than radix-2 and radix-4 FFT algorithms, and is comparable to Split radix FFT algorithm, in terms of computational requirements. Different architectures are proposed for DFT processing module, and their comparative analysis is done. ASIC implementation of Discrete Fourier Transform processing module includes, its modelling using Verilog HDL, gate level synthesis of the modelled design and physical synthesis of netlist generated by gate level synthesis. The functionality of Design after physical synthesis is verified. Designed DFT processing module is retargetable and can be used as an IP.
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    Architecture design for preliminary ECG analysis system using new DFT based analysis technique
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Chaurey, Vasudha; Nagchoudhuri, Dipankar
    This thesis proposes a hardware architecture of an ASIC for a portable ECG analysis system. The device is meant to record and analyze ECG signals in real time so as to detect the presence of abnormalities. In order to achieve this, a totally new approach for the analysis of ECG signals using Discrete Fourier Transform (DFT) is developed as a part of the thesis. An important finding of the project, through experiments performed on real ECG data in MATLAB, is that the phases of first 8 DFT coefficients of beat-wise ECG signals give distinguishing patterns for normal and abnormal beats. With this idea of variable size DFT as the basis, a much simplified form of the technique with fixed 32 point DFT is derived without significantly disturbing the patterns so as to make it suitable for hardware implementation. The translation of the algorithm to hardware architecture has been done in a way so as to achieve optimization in terms of area as well as power by minimizing the number of computations. One of the important features of the proposed architecture is the synchronization of the complete system which processes an asynchronous signal, i.e. the ECG beats, in real time. The thesis gives the custom Register Transfer Level architecture for the processing block of the system, which is meant for selecting fixed number of samples from every beat and do a customized DFT phase computation for detecting abnormalities. The project proposes a very simple technique for the beat detection as a part of optimization. Since the incoming signal is much slower than the processing rate, the proposed architecture is designed with the flexibility of adding extra functionalities in the system other than ECG analysis which if possible can use the same processing hardware during the wait periods.