M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

Browse

Filters

2008 - 200912010 - 20121

Settings

Has files: YesSubject: search.filters.subject.Reliability

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    ItemOpen Access
    Application of compressive sensing to tow-way relay channel estimation
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Nair, Rahit R.; Chakka, Vijaykumar
    An Amplify and Forward Two-Way Relay Network is one where two nodes transmit data to each other via an intermediate relay. The relay amplifies the superimposed data from both the nodes before sending it to both the nodes. A method for the estimation of channel is proposed for Amplify and Forward Two-Way Relay Network (AF-TWRN). The proposed method utilizes the fact that the channel in the case of AF-TWRN shows sparse characteristic. The sparse multipath channel is estimated in the case of AF-TWRN using compressive sensing (CS) reconstruction algorithm, namely Iterative Hard Thresholding (IHT). MSE based performance of these methods in estimating the composite AF-TWRN channel was calculated and compared to that using Compressive Sampling Matching Pursuit (CoSaMP) and Orthogonal Matching Pursuit (OMP). IHT and CoSaMP are seen to perform slightly better than OMP with lesser computational complexity than OMP. It was also shown that all three CS based estimation methods perform better than the traditional Least Squares (LS) method in the estimation of Sparse AF-TWRN channel. A low complexity detection strategy was proposed
  • Thumbnail Image
    ItemOpen Access
    Improvement of tagged architecture for preventing software vulnerabilities
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Shah, Tejaskumar; Mathuria, Anish M.
    In spite of the many defense techniques, software vulnerabilities like buffer overflow, format string vulnerability and integer vulnerability is still exploited by attackers. These software vulnerabilities arise due to programming mistakes which allows security bugs to be exploited. Buffer overflow occurs when buffer is given more data than the capacity of it. Format string vulnerability arises when data supplied by attacker is passed to formatting functions as format string argument. Integer vulnerability occurs when program evaluates an integer to unexpected value due to integer overflows, underflows, truncation errors or signed conversion errors. The hardware based solution called tagged architecture protects a system against mentioned vulnerabilities. In tagged architecture, each memory byte is appended with one tag bit to mark data that comes from I/O. Whenever I/O supplied data is used to transfer control of a system or to access memory, an alert is raised and program is terminated. This thesis proposes a weakness of tagged architecture by finding false positives and false negatives on it. It also proposes the improvements to the tagged architecture to avoid found false positives on it. The prototype implementation of improved tagged architecture is done in SimpleScalar simulator. The SimpleScalar simulator is a architectural simulator. The security evaluation is done for tagged architecture and improved tagged architecture through benchmarks and synthetic vulnerable programs.