M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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    Analysis of various DFT techniques in the ASIC designs
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Rathod, Gayatri Manohar; Bhatt, Amit
    With the increasing demand of mobile communication industry and highly progressive VLSI technology, muti-million gates silicon chips are in the market. And to have fault free, reliable chips, extended facility of testable circuit has to be added into the original design. The design technique which includes the testability logic into the design at the logical synthesis level is known as Design for Test abbreviated as DFT [1]. To achieve better fault coverage, I have chosen full scan chain insertion technique for OR1200 design. OR1200 is a 32-bit microprocessor with 5-stage pipeline [12]. Its RTL code is taken from opencores.org and Cadence RTL Compiler version 11.1 is used for logic synthesis. For testing and verification, Encounter Test Version 11.1 and NCVerilog simulator is used. To improve the testability of the design, Deterministic fault analysis and Random Resistant Fault Analysis techniques are also added to the design. Effects of all hardware DFT techniques are analysed in terms of area, dynamic power dissipation and gate count. Main low power technique i.e. clock gating is also inserted along with DFT to achieve better performance in terms of power dissipation. DFT causes 25% of increase in die area and 12% of increase in dynamic power. This is acceptable as we will get OR1200 design with 99.67% fault coverage area.
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    Reduction of power using innovative Clock Gating and Multi Vth techniques in digital design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Sharma, Dushyant Kumar; Bhatt, Amit
    Low power is one of the most important issues in today’s ASIC (Application Specific Integrated Circuit) design. As the transistors scale down, power density becomes high and there is immediate need of reduction in power. There are different techniques available for reduction of power like Operand isolation (OI), Clock Gating (CG) and Multi Vth Library Utilization (MVLU). In this report, we present two approaches for power reduction. The first approach gives two algorithms that show how power and performance matrix is improved compared to conventional MVLU technique. In the second approach, it shows the implementation of constrained fanout clock gating and its benefits over conventional clock gating techniques in ASIC design methodology. This report also presents two analyses. The first analysis shows how the design metrics area, power and performance change due to different techniques of low power (Operand Isolation, Clock Gating and Multi Vth Cell Utilization). The second analysis demonstrates the effect of different CG cells in design and presents how the same design metrics are affected for each CG cell. There are two variations in each CG cell, one is with Reset and the other is without Reset. In this report, we also demonstrate how the design metrics are affected by insertion of Reset signal in each CG cell
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    Realization of FPGA based digital controller
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Patel, Amit; Dubey, Rahul
    Field Programmable Gate Array (FPGA) can be used to enhance the efficiency and the flexibility of digital controller. FPGA implementation of digital controllers leads to real time realizations with small size and high speed. Also it offers advantages such as complex functionality, fast computation, and low power consumption for high volume production. This thesis presents realization of FPGA based speed control of brushless dc (BLDC) motor - a real time application. The construction and the operation of the BLDC motor are described. The different control strategies for speed controller and digital pulse width modulation (PWM) control technique are implemented and tested on BLDC motor. Also their performance is evaluated. Proportional Integral (PI) controller and Fuzzy Logic Controller (FLC) are implemented in FPGA as a digital controller. The PI controller is governed by the values of proportional gain and integral gain, while FLC behaves in much similar way as human controls the system. Logics of both controllers: PI controller and fuzzy logic controller are written in High Description Language (HDL). The performance of the PI controller is better than the fuzzy logic controller in case of the complete known plant.